Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

[oweals/u-boot.git] / arch / x86 / cpu / ivybridge / sdram.c

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 8a58d0383d506e29f12773a6766fe3d998804df0..99bc48021e6900fdb439fc2b1e8e04de99dfa93e 100644 (file)
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -12,6 +12,8 @@
 #include <common.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <init.h>
+#include <log.h>
 #include <malloc.h>
 #include <net.h>
 #include <rtc.h>
@@ -115,7 +117,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
        ret = read_seed_from_cmos(pei_data);
        if (ret)
                return ret;
-       ret = mrccache_get_region(NULL, &entry);
+       ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
        if (ret)
                return ret;
        mrc_cache = mrccache_find_current(&entry);
@@ -537,12 +539,14 @@ int dram_init(void)
 
        /* S3 resume: don't save scrambler seed or MRC data */
        if (pei_data->boot_mode != PEI_BOOT_RESUME) {
+               struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
+
                /*
                 * This will be copied to SDRAM in reserve_arch(), then written
                 * to SPI flash in mrccache_save()
                 */
-               gd->arch.mrc_output = (char *)pei_data->mrc_output;
-               gd->arch.mrc_output_len = pei_data->mrc_output_len;
+               mrc->buf = (char *)pei_data->mrc_output;
+               mrc->len = pei_data->mrc_output_len;
                ret = write_seeds_to_cmos(pei_data);
                if (ret)
                        debug("Failed to write seeds to CMOS: %d\n", ret);