Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / x86 / cpu / ivybridge / sata.c

diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index a59d9edce5f57edd2c4167404cc27247c68b1304..025b20be31bd1137854c2565e3a25650b15081e9 100644 (file)
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -1,36 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * From Coreboot
  * Copyright (C) 2008-2009 coresystems GmbH
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <common.h>
+#include <ahci.h>
 #include <dm.h>
 #include <fdtdec.h>
+#include <log.h>
 #include <asm/io.h>
+#include <asm/pch_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
-#include <asm/arch/bd82x6x.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static inline u32 sir_read(struct udevice *dev, int idx)
-{
-       u32 data;
-
-       dm_pci_write_config32(dev, SATA_SIRI, idx);
-       dm_pci_read_config32(dev, SATA_SIRD, &data);
-
-       return data;
-}
-
-static inline void sir_write(struct udevice *dev, int idx, u32 value)
-{
-       dm_pci_write_config32(dev, SATA_SIRI, idx);
-       dm_pci_write_config32(dev, SATA_SIRD, value);
-}
-
 static void common_sata_init(struct udevice *dev, unsigned int port_map)
 {
        u32 reg32;
@@ -55,7 +40,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 {
        unsigned int port_map, speed_support, port_tx;
        const void *blob = gd->fdt_blob;
-       int node = dev->of_offset;
+       int node = dev_of_offset(dev);
        const char *mode;
        u32 reg32;
        u16 reg16;
@@ -69,7 +54,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 
        mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
        if (!mode || !strcmp(mode, "ahci")) {
-               u32 abar;
+               ulong abar;
 
                debug("SATA: Controller in AHCI mode\n");
 
@@ -88,7 +73,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 
                /* Initialize AHCI memory-mapped space */
                abar = dm_pci_read_bar32(dev, 5);
-               debug("ABAR: %08X\n", abar);
+               debug("ABAR: %08lx\n", abar);
                /* CAP (HBA Capabilities) : enable power management */
                reg32 = readl(abar + 0x00);
                reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
@@ -177,27 +162,27 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
                pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
 
        /* Additional Programming Requirements */
-       sir_write(dev, 0x04, 0x00001600);
-       sir_write(dev, 0x28, 0xa0000033);
-       reg32 = sir_read(dev, 0x54);
+       pch_common_sir_write(dev, 0x04, 0x00001600);
+       pch_common_sir_write(dev, 0x28, 0xa0000033);
+       reg32 = pch_common_sir_read(dev, 0x54);
        reg32 &= 0xff000000;
        reg32 |= 0x5555aa;
-       sir_write(dev, 0x54, reg32);
-       sir_write(dev, 0x64, 0xcccc8484);
-       reg32 = sir_read(dev, 0x68);
+       pch_common_sir_write(dev, 0x54, reg32);
+       pch_common_sir_write(dev, 0x64, 0xcccc8484);
+       reg32 = pch_common_sir_read(dev, 0x68);
        reg32 &= 0xffff0000;
        reg32 |= 0xcccc;
-       sir_write(dev, 0x68, reg32);
-       reg32 = sir_read(dev, 0x78);
+       pch_common_sir_write(dev, 0x68, reg32);
+       reg32 = pch_common_sir_read(dev, 0x78);
        reg32 &= 0x0000ffff;
        reg32 |= 0x88880000;
-       sir_write(dev, 0x78, reg32);
-       sir_write(dev, 0x84, 0x001c7000);
-       sir_write(dev, 0x88, 0x88338822);
-       sir_write(dev, 0xa0, 0x001c7000);
-       sir_write(dev, 0xc4, 0x0c0c0c0c);
-       sir_write(dev, 0xc8, 0x0c0c0c0c);
-       sir_write(dev, 0xd4, 0x10000000);
+       pch_common_sir_write(dev, 0x78, reg32);
+       pch_common_sir_write(dev, 0x84, 0x001c7000);
+       pch_common_sir_write(dev, 0x88, 0x88338822);
+       pch_common_sir_write(dev, 0xa0, 0x001c7000);
+       pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
+       pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
+       pch_common_sir_write(dev, 0xd4, 0x10000000);
 
        pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
        pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
@@ -206,7 +191,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 static void bd82x6x_sata_enable(struct udevice *dev)
 {
        const void *blob = gd->fdt_blob;
-       int node = dev->of_offset;
+       int node = dev_of_offset(dev);
        unsigned port_map;
        const char *mode;
        u16 map = 0;
@@ -224,21 +209,37 @@ static void bd82x6x_sata_enable(struct udevice *dev)
        dm_pci_write_config16(dev, 0x90, map);
 }
 
+static int bd82x6x_sata_bind(struct udevice *dev)
+{
+       struct udevice *scsi_dev;
+       int ret;
+
+       if (gd->flags & GD_FLG_RELOC) {
+               ret = ahci_bind_scsi(dev, &scsi_dev);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
 static int bd82x6x_sata_probe(struct udevice *dev)
 {
        struct udevice *pch;
        int ret;
 
-       ret = uclass_first_device(UCLASS_PCH, &pch);
+       ret = uclass_first_device_err(UCLASS_PCH, &pch);
        if (ret)
                return ret;
-       if (!pch)
-               return -ENODEV;
 
        if (!(gd->flags & GD_FLG_RELOC))
                bd82x6x_sata_enable(dev);
-       else
+       else {
                bd82x6x_sata_init(dev, pch);
+               ret = ahci_probe_scsi_pci(dev);
+               if (ret)
+                       return ret;
+       }
 
        return 0;
 }
@@ -250,7 +251,8 @@ static const struct udevice_id bd82x6x_ahci_ids[] = {
 
 U_BOOT_DRIVER(ahci_ivybridge_drv) = {
        .name           = "ahci_ivybridge",
-       .id             = UCLASS_DISK,
+       .id             = UCLASS_AHCI,
        .of_match       = bd82x6x_ahci_ids,
+       .bind           = bd82x6x_sata_bind,
        .probe          = bd82x6x_sata_probe,
 };