+// SPDX-License-Identifier: GPL-2.0
/*
* From coreboot southbridge/intel/bd82x6x/lpc.c
*
* Copyright (C) 2008-2009 coresystems GmbH
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <log.h>
#include <rtc.h>
#include <pci.h>
#include <asm/intel_regs.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
{
uint8_t route[8], *ptr;
- if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
"intel,pirq-routing", route, sizeof(route)))
return -EINVAL;
ptr = route;
u32 reg;
int gpi;
- if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
"intel,gpi-routing", route, sizeof(route)))
return -EINVAL;
static int pch_power_options(struct udevice *pch)
{
const void *blob = gd->fdt_blob;
- int node = pch->of_offset;
+ int node = dev_of_offset(pch);
u8 reg8;
u16 reg16, pmbase;
u32 reg32;
dm_pci_read_config16(pch, 0x40, &pmbase);
pmbase &= 0xfffe;
- writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
- "intel,gpe0-enable", 0));
- writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
- "intel,alt-gp-smi-enable", 0));
+ writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
+ (ulong)pmbase + GPE0_EN);
+ writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
+ (ulong)pmbase + ALT_GP_SMI_EN);
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); /* PM1_CNT */
reg16 |= (1 << 2) | (1 << 11);
dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
- pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
- pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
- pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
- pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
+ pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
+ pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
+ pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
+ pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
reg32 = readl(RCB_REG(CG));
reg32 |= (1 << 31);
static int lpc_init_extra(struct udevice *dev)
{
struct udevice *pch = dev->parent;
- const void *blob = gd->fdt_blob;
- int node;
debug("pch: lpc_init\n");
dm_pci_write_bar32(pch, 0, 0);
dm_pci_write_bar32(pch, 3, 0x800);
dm_pci_write_bar32(pch, 4, 0x900);
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
- if (node < 0)
- return -ENOENT;
-
/* Set the value for PCI command register. */
dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);