Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / x86 / cpu / ivybridge / bd82x6x.c

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 5b58d6c427e9a1547798b867cb4f363840dc522b..5448f064fcbf0761da5ba445b396c6d7baaf68bb 100644 (file)
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -1,28 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014 Google, Inc
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <log.h>
 #include <malloc.h>
 #include <pch.h>
-#include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/lpc_common.h>
 #include <asm/pci.h>
-#include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_BASE              0x48
+#define BIOS_CTRL              0xdc
 
-#define GPIO_BASE      0x48
-#define BIOS_CTRL      0xdc
+#define RCBA_AUDIO_CONFIG      0x2030
+#define RCBA_AUDIO_CONFIG_HDA  BIT(31)
+#define RCBA_AUDIO_CONFIG_MASK 0xfe
 
 #ifndef CONFIG_HAVE_FSP
 static int pch_revision_id = -1;
@@ -155,22 +161,12 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
 
 static int bd82x6x_probe(struct udevice *dev)
 {
-       struct udevice *gma_dev;
-       int ret;
-
        if (!(gd->flags & GD_FLG_RELOC))
                return 0;
 
        /* Cause the SATA device to do its init */
        uclass_first_device(UCLASS_AHCI, &dev);
 
-       ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
-       if (ret)
-               return ret;
-       ret = gma_func0_init(gma_dev);
-       if (ret)
-               return ret;
-
        return 0;
 }
 #endif /* CONFIG_HAVE_FSP */
@@ -223,10 +219,44 @@ static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
        return 0;
 }
 
+static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data,
+                        int size)
+{
+       u32 rcba, val;
+
+       switch (req) {
+       case PCH_REQ_HDA_CONFIG:
+               dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+               val = readl(rcba + RCBA_AUDIO_CONFIG);
+               if (!(val & RCBA_AUDIO_CONFIG_HDA))
+                       return -ENOENT;
+
+               return val & RCBA_AUDIO_CONFIG_MASK;
+       case PCH_REQ_PMBASE_INFO: {
+               struct pch_pmbase_info *pm = data;
+               int ret;
+
+               /* Find the base address of the powermanagement registers */
+               ret = dm_pci_read_config16(dev, 0x40, &pm->base);
+               if (ret)
+                       return ret;
+               pm->base &= 0xfffe;
+               pm->gpio0_en_ofs = GPE0_EN;
+               pm->pm1_sts_ofs = PM1_STS;
+               pm->pm1_cnt_ofs = PM1_CNT;
+
+               return 0;
+       }
+       default:
+               return -ENOSYS;
+       }
+}
+
 static const struct pch_ops bd82x6x_pch_ops = {
        .get_spi_base   = bd82x6x_pch_get_spi_base,
        .set_spi_protect = bd82x6x_set_spi_protect,
        .get_gpio_base  = bd82x6x_get_gpio_base,
+       .ioctl          = bd82x6x_ioctl,
 };
 
 static const struct udevice_id bd82x6x_ids[] = {