Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / x86 / cpu / cpu.c

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index c9fc7e4ebf10aaa7a06400dfdd72b280522571b6..a814e7d7a649896c0c13e945dc9392bd54e543f5 100644 (file)
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2008-2011
  * Graeme Russ, <graeme.russ@gmail.com>
@@ -15,18 +16,21 @@
  *
  * Part of this file is adapted from coreboot
  * src/arch/x86/lib/cpu.c
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <bootstage.h>
 #include <command.h>
+#include <cpu_func.h>
 #include <dm.h>
 #include <errno.h>
+#include <init.h>
+#include <log.h>
 #include <malloc.h>
 #include <syscon.h>
-#include <asm/acpi_s3.h>
-#include <asm/acpi_table.h>
+#include <acpi/acpi_s3.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi.h>
 #include <asm/control_regs.h>
 #include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
@@ -45,6 +49,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_TPL_BUILD
 static const char *const x86_vendor_name[] = {
        [X86_VENDOR_INTEL]     = "Intel",
        [X86_VENDOR_CYRIX]     = "Cyrix",
@@ -57,6 +62,7 @@ static const char *const x86_vendor_name[] = {
        [X86_VENDOR_NSC]       = "NSC",
        [X86_VENDOR_SIS]       = "SiS",
 };
+#endif
 
 int __weak x86_cleanup_before_linux(void)
 {
@@ -76,37 +82,11 @@ int x86_init_cache(void)
 }
 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       printf("resetting ...\n");
-
-       /* wait 50 ms */
-       udelay(50000);
-       disable_interrupts();
-       reset_cpu(0);
-
-       /*NOTREACHED*/
-       return 0;
-}
-
 void  flush_cache(unsigned long dummy1, unsigned long dummy2)
 {
        asm("wbinvd\n");
 }
 
-__weak void reset_cpu(ulong addr)
-{
-       /* Do a hard reset through the chipset's reset control register */
-       outb(SYS_RST | RST_CPU, IO_PORT_RESET);
-       for (;;)
-               cpu_hlt();
-}
-
-void x86_full_reset(void)
-{
-       outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
-}
-
 /* Define these functions to allow ehch-hcd to function */
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
@@ -139,16 +119,18 @@ int icache_status(void)
        return 1;
 }
 
+#ifndef CONFIG_TPL_BUILD
 const char *cpu_vendor_name(int vendor)
 {
        const char *name;
        name = "<invalid cpu vendor>";
-       if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
-           (x86_vendor_name[vendor] != 0))
+       if (vendor < ARRAY_SIZE(x86_vendor_name) &&
+           x86_vendor_name[vendor])
                name = x86_vendor_name[vendor];
 
        return name;
 }
+#endif
 
 char *cpu_get_name(char *name)
 {
@@ -194,7 +176,7 @@ void show_boot_progress(int val)
        outb(val, POST_PORT);
 }
 
-#ifndef CONFIG_SYS_COREBOOT
+#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
 /*
  * Implement a weak default function for boards that optionally
  * need to clean up the system before jumping to the kernel.
@@ -205,17 +187,32 @@ __weak void board_final_cleanup(void)
 
 int last_stage_init(void)
 {
+       struct acpi_fadt __maybe_unused *fadt;
+
        board_final_cleanup();
 
-#if CONFIG_HAVE_ACPI_RESUME
-       void *wake_vector = acpi_find_wakeup_vector();
+#ifdef CONFIG_HAVE_ACPI_RESUME
+       fadt = acpi_find_fadt();
 
-       if (wake_vector != NULL && gd->arch.prev_sleep_state == ACPI_S3)
-               acpi_resume(wake_vector);
+       if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
+               acpi_resume(fadt);
 #endif
 
        write_tables();
 
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+       fadt = acpi_find_fadt();
+
+       /* Don't touch ACPI hardware on HW reduced platforms */
+       if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
+               /*
+                * Other than waiting for OSPM to request us to switch to ACPI
+                * mode, do it by ourselves, since SMI will not be triggered.
+                */
+               enter_acpi_mode(fadt->pm1a_cnt_blk);
+       }
+#endif
+
        return 0;
 }
 #endif
@@ -244,8 +241,10 @@ int cpu_init_r(void)
        struct udevice *dev;
        int ret;
 
-       if (!ll_boot_init())
+       if (!ll_boot_init()) {
+               uclass_first_device(UCLASS_PCI, &dev);
                return 0;
+       }
 
        ret = x86_init_cpus();
        if (ret)
@@ -278,14 +277,43 @@ int reserve_arch(void)
        high_table_reserve();
 #endif
 
-#if defined(CONFIG_HAVE_ACPI_RESUME) && defined(CONFIG_HAVE_FSP)
+#ifdef CONFIG_HAVE_ACPI_RESUME
+       acpi_s3_reserve();
+
+#ifdef CONFIG_HAVE_FSP
        /*
         * Save stack address to CMOS so that at next S3 boot,
         * we can use it as the stack address for fsp_contiue()
         */
        fsp_save_s3_stack();
-#endif
+#endif /* CONFIG_HAVE_FSP */
+#endif /* CONFIG_HAVE_ACPI_RESUME */
 
        return 0;
 }
 #endif
+
+long detect_coreboot_table_at(ulong start, ulong size)
+{
+       u32 *ptr, *end;
+
+       size /= 4;
+       for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+               if (*ptr == 0x4f49424c) /* "LBIO" */
+                       return (long)ptr;
+       }
+
+       return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+       long addr;
+
+       /* We look for LBIO in the first 4K of RAM and again at 960KB */
+       addr = detect_coreboot_table_at(0x0, 0x1000);
+       if (addr < 0)
+               addr = detect_coreboot_table_at(0xf0000, 0x1000);
+
+       return addr;
+}