Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0faaac1a98a00ac9e1b364f4016a05afaf..fb5fe5affff1f3979279d030113872aee9755418 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+       prompt "SPL Run Mode"
+       default SPL_RISCV_MMODE
+       depends on SPL
+
+config SPL_RISCV_MMODE
+       bool "Machine"
+       help
+         Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+       bool "Supervisor"
+       help
+         Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
        bool "Emit compressed instructions"
        default y
@@ -132,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The SiFive CLINT block holds memory-mapped control and status registers
          associated with software and timer interrupts.
 
 config ANDES_PLIC
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLIC block holds memory-mapped claim and pending registers
          associated with software interrupt.
 
 config ANDES_PLMT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLMT block holds memory-mapped mtime register
          associated with timer tick.
 
 config RISCV_RDTIME
        bool
-       default y if RISCV_SMODE
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        help
          The provides the riscv_get_time() API that is implemented using the
          standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -170,6 +193,7 @@ config SYS_MALLOC_F_LEN
 
 config SMP
        bool "Symmetric Multi-Processing"
+       depends on SBI_V01 || !RISCV_SMODE
        help
          This enables support for systems with more than one CPU. If
          you say N here, U-Boot will run on single and multiprocessor
@@ -177,19 +201,61 @@ config SMP
          machine. If you say Y here, U-Boot will run on many, but not
          all, single processor machines.
 
+config SPL_SMP
+       bool "Symmetric Multi-Processing in SPL"
+       depends on SPL && SPL_RISCV_MMODE
+       default y
+       help
+         This enables support for systems with more than one CPU in SPL.
+         If you say N here, U-Boot SPL will run on single and multiprocessor
+         machines, but will use only one CPU of a multiprocessor
+         machine. If you say Y here, U-Boot SPL will run on many, but not
+         all, single processor machines.
+
 config NR_CPUS
        int "Maximum number of CPUs (2-32)"
        range 2 32
-       depends on SMP
+       depends on SMP || SPL_SMP
        default 8
        help
          On multiprocessor machines, U-Boot sets up a stack for each CPU.
          Stack memory is pre-allocated. U-Boot must therefore know the
          maximum number of CPUs that may be present.
 
+config SBI
+       bool
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
+
+choice
+       prompt "SBI support"
+       default SBI_V02
+
+config SBI_V01
+       bool "SBI v0.1 support"
+       depends on SBI
+       help
+         This config allows kernel to use SBI v0.1 APIs. This will be
+         deprecated in future once legacy M-mode software are no longer in use.
+
+config SBI_V02
+       bool "SBI v0.2 support"
+       depends on SBI
+       help
+         This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
+         scalable and extendable to handle future needs for RISC-V supervisor
+         interfaces. For example, with SBI v0.2 HSM extension, only a single
+         hart need to boot and enter operating system. The booting hart can
+         bring up secondary harts one by one afterwards.
+
+         Choose this option if OpenSBI v0.7 or above release is used together
+         with U-Boot.
+
+endchoice
+
 config SBI_IPI
        bool
-       default y if RISCV_SMODE
+       depends on SBI
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        depends on SMP
 
 config XIP
@@ -199,8 +265,11 @@ config XIP
          from a NOR flash memory without copying the code to ram.
          Say yes here if U-Boot boots from flash directly.
 
+config SHOW_REGS
+       bool "Show registers on unhandled exception"
+
 config STACK_SIZE_SHIFT
        int
-       default 13
+       default 14
 
 endmenu