Merge branch 'next' of git://git.denx.de/u-boot-usb into next

[oweals/u-boot.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0faaac1a98a00ac9e1b364f4016a05afaf..3061bf886302ba1c71fec336cfdd3a641973efc7 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+       prompt "SPL Run Mode"
+       default SPL_RISCV_MMODE
+       depends on SPL
+
+config SPL_RISCV_MMODE
+       bool "Machine"
+       help
+         Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+       bool "Supervisor"
+       help
+         Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
        bool "Emit compressed instructions"
        default y
@@ -132,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The SiFive CLINT block holds memory-mapped control and status registers
          associated with software and timer interrupts.
 
 config ANDES_PLIC
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLIC block holds memory-mapped claim and pending registers
          associated with software interrupt.
 
 config ANDES_PLMT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLMT block holds memory-mapped mtime register
          associated with timer tick.
 
 config RISCV_RDTIME
        bool
-       default y if RISCV_SMODE
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        help
          The provides the riscv_get_time() API that is implemented using the
          standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -187,9 +210,22 @@ config NR_CPUS
          Stack memory is pre-allocated. U-Boot must therefore know the
          maximum number of CPUs that may be present.
 
+config SBI
+       bool
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
+
+config SBI_V01
+       bool "SBI v0.1 support"
+       default y
+       depends on SBI
+       help
+         This config allows kernel to use SBI v0.1 APIs. This will be
+         deprecated in future once legacy M-mode software are no longer in use.
+
 config SBI_IPI
        bool
-       default y if RISCV_SMODE
+       depends on SBI
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        depends on SMP
 
 config XIP
@@ -199,8 +235,11 @@ config XIP
          from a NOR flash memory without copying the code to ram.
          Say yes here if U-Boot boots from flash directly.
 
+config SHOW_REGS
+       bool "Show registers on unhandled exception"
+
 config STACK_SIZE_SHIFT
        int
-       default 13
+       default 14
 
 endmenu