+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <log.h>
#include <asm/processor.h>
+#include <env.h>
#include <ioports.h>
#include <lmb.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
+#include <linux/delay.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
*/
int hold_cores_in_reset(int verbose)
{
- /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
- if (getenv_yesno("mp_holdoff") == 1) {
+ /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
+ if (env_get_yesno("mp_holdoff") == 1) {
if (verbose) {
puts("Secondary cores are being held in reset.\n");
puts("See 'mp_holdoff' environment variable\n");
return 0;
}
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
{
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr);
return 0;
}
-int cpu_status(int nr)
+int cpu_status(u32 nr)
{
u32 *table, id = get_my_id();
}
#ifdef CONFIG_FSL_CORENET
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
return (coredisrl & (1 << nr));
}
#else
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
BOOT_ENTRY_R3_LOWER,
};
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char *const argv[])
{
u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
u64 boot_addr;