+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <irq_func.h>
+#include <log.h>
+#include <time.h>
+#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
#include <fsl_esdhc.h>
#include <post.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
+#include <asm/ppc.h>
+#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int i, core, nr_cores = cpu_numcores();
u32 mask = cpu_mask();
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
+ u32 dsp_mask = cpu_dsp_mask();
+#endif
+
svr = get_svr();
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
printf("CPU%d:%-4s MHz, ", core,
strmhz(buf1, sysinfo.freq_processor[core]));
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
+ if (!(j & 3))
+ printf("\n ");
+ printf("DSP CPU%d:%-4s MHz, ", j,
+ strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
+ }
+#endif
+
printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
printf("\n");
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
+#if defined(CONFIG_SYS_CPRI)
+ printf(" ");
+ printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
+#endif
+
+#if defined(CONFIG_SYS_MAPLE)
+ printf("\n ");
+ printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
+ printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
+ printf("MAPLE-eTVPE:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freq_maple_etvpe));
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
-__weak unsigned long get_tbclk (void)
+__weak unsigned long get_tbclk(void)
{
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
#if defined(CONFIG_WATCHDOG)
+#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
+void
+init_85xx_watchdog(void)
+{
+ mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
+ TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
+}
+
void
reset_85xx_watchdog(void)
{
* Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
* parameters for IFC and TLBs
*/
-void mpc85xx_reginfo(void)
+void print_reginfo(void)
{
print_tlbcam();
print_laws();
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
- defined(CONFIG_QEMU_E500)
- return fsl_ddr_sdram_size();
+ defined(CONFIG_ARCH_QEMU_E500)
+ gd->ram_size = fsl_ddr_sdram_size();
#else
- return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
+
+ return 0;
}
#else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
phys_size_t dram_size = 0;
#endif
debug("DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif
/* Board-specific functions defined in each board's ddr.c */
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num);
+ unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn);
unsigned int
int i, j, k, m;
u8 *p_8;
u32 *p_32;
- struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
generic_spd_eeprom_t
- spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+ spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
- fsl_ddr_get_spd(spd[i], i);
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
+ fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
- puts("SPD data of all dimms (zero vaule is omitted)...\n");
+ puts("SPD data of all dimms (zero value is omitted)...\n");
puts("Byte (hex) ");
k = 1;
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
printf("Dimm%d ", k++);
}
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
m = 0;
printf("%3d (0x%02x) ", k, k);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
p_8 = (u8 *) &spd[i][j];
if (p_8[k]) {
puts("\r");
}
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
}
}
printf("DDR registers dump for all controllers "
- "(zero vaule is omitted)...\n");
+ "(zero value is omitted)...\n");
puts("Offset (hex) ");
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
p_32 = (u32 *) ddr[i];
if (p_32[k]) {
printf(" 0x%08x", p_32[k]);
projects / oweals / u-boot.git / blobdiff