Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

[oweals/u-boot.git] / arch / powerpc / cpu / mpc83xx / spd_sdram.c

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 97ef77121b5a6c6a356fa6eacd79a94d866daf75..aeff007fb0639eff57b93a77bd1552ca75c32e3d 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -13,12 +13,18 @@
 #ifndef CONFIG_MPC83XX_SDRAM
 
 #include <common.h>
+#include <cpu_func.h>
+#include <log.h>
+#include <time.h>
+#include <vsprintf.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <i2c.h>
 #include <spd.h>
 #include <asm/mmu.h>
 #include <spd_sdram.h>
+#include <asm/bitops.h>
+#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -31,7 +37,7 @@ void board_add_ram_info(int use_default)
        printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
                           >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
 
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
        if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
                puts(", 16-bit");
        else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
@@ -281,7 +287,7 @@ long int spd_sdram()
        /*
         * Set up LAWBAR for all of DDR.
         */
-       ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+       ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
        ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
        debug("DDR:bar=0x%08x\n", ecm->bar);
        debug("DDR:ar=0x%08x\n", ecm->ar);
@@ -426,7 +432,7 @@ long int spd_sdram()
 
        /*
         * Errata DDR6 work around: input enable 2 cycles earlier.
-        * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
+        * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
         */
        if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
                if (caslat == 2)
@@ -436,7 +442,7 @@ long int spd_sdram()
                else if (caslat == 4)
                        ddr->debug_reg = 0x202c0000; /* CL=3.0 */
 
-               __asm__ __volatile__ ("sync");
+               sync();
 
                debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
        }
@@ -765,7 +771,8 @@ long int spd_sdram()
 #endif
        debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
-       asm("sync;isync");
+       sync();
+       isync();
 
        udelay(600);
 
@@ -834,7 +841,8 @@ long int spd_sdram()
 #endif
        /* Enable controller, and GO! */
        ddr->sdram_cfg = sdram_cfg;
-       asm("sync;isync");
+       sync();
+       isync();
        udelay(500);
 
        debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
@@ -843,6 +851,22 @@ long int spd_sdram()
 #endif /* CONFIG_SPD_EEPROM */
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+static inline u32 mftbu(void)
+{
+       u32 rval;
+
+       asm volatile("mftbu %0" : "=r" (rval));
+       return rval;
+}
+
+static inline u32 mftb(void)
+{
+       u32 rval;
+
+       asm volatile("mftb %0" : "=r" (rval));
+       return rval;
+}
+
 /*
  * Use timebase counter, get_timer() is not available
  * at this point of initialization yet.
@@ -858,9 +882,9 @@ static __inline__ unsigned long get_tbms (void)
 
        /* get the timebase ticks */
        do {
-               asm volatile ("mftbu %0":"=r" (tbu1):);
-               asm volatile ("mftb %0":"=r" (tbl):);
-               asm volatile ("mftbu %0":"=r" (tbu2):);
+               tbu1 = mftbu();
+               tbl = mftb();
+               tbu2 = mftbu();
        } while (tbu1 != tbu2);
 
        /* convert ticks to ms */
@@ -897,7 +921,7 @@ void ddr_enable_ecc(unsigned int dram_size)
        for (p = 0; p < (u64*)(size); p++) {
                ppcDWstore((u32*)p, pattern);
        }
-       __asm__ __volatile__ ("sync");
+       sync();
 #endif
 
        t_end = get_tbms();
@@ -922,8 +946,8 @@ void ddr_enable_ecc(unsigned int dram_size)
        /* Enable errors for ECC */
        ddr->err_disable &= ECC_ERROR_ENABLE;
 
-       __asm__ __volatile__ ("sync");
-       __asm__ __volatile__ ("isync");
+       sync();
+       isync();
 }
 #endif /* CONFIG_DDR_ECC */