Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / powerpc / cpu / mpc83xx / serdes.c

diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c
index 64033fe4c35dec86b046f6f745ba122d0bc7fc65..bb963ee5e2f4826580b063103f13ea833e435327 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/serdes.c
+++ b/arch/powerpc/cpu/mpc83xx/serdes.c
@@ -1,25 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Freescale SerDes initialization routine
  *
- * Copyright (C) 2007 Freescale Semicondutor, Inc.
+ * Copyright 2007,2011 Freescale Semiconductor, Inc.
  * Copyright (C) 2008 MontaVista Software, Inc.
  *
  * Author: Li Yang <leoli@freescale.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
  */
 
+#ifndef CONFIG_MPC83XX_SERDES
+
 #include <config.h>
 #include <common.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <linux/delay.h>
 
 /* SerDes registers */
 #define FSL_SRDSCR0_OFFS               0x0
 #define FSL_SRDSCR0_DPP_1V2            0x00008800
+#define FSL_SRDSCR0_TXEQA_MASK         0x00007000
+#define FSL_SRDSCR0_TXEQA_SATA         0x00001000
+#define FSL_SRDSCR0_TXEQE_MASK         0x00000700
+#define FSL_SRDSCR0_TXEQE_SATA         0x00000100
 #define FSL_SRDSCR1_OFFS               0x4
 #define FSL_SRDSCR1_PLLBW              0x00000040
 #define FSL_SRDSCR2_OFFS               0x8
@@ -71,6 +74,11 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
                tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
                out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
 
+               /* Configure SRDSCR0 */
+               clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
+                       FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
+                       FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
+
                /* Configure SRDSCR1 */
                tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
                tmp &= ~FSL_SRDSCR1_PLLBW;
@@ -143,3 +151,5 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
        tmp |= FSL_SRDSRSTCTL_RST;
        out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
 }
+
+#endif /* !CONFIG_MPC83XX_SERDES */