*/
#include <common.h>
+#include <asm-offsets.h>
#include <mpc83xx.h>
#include <ioports.h>
#include <asm/io.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-ci.h>
#endif
+#include <linux/delay.h>
+
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
DECLARE_GLOBAL_DATA_PTR;
*/
void cpu_init_f (volatile immap_t * im)
{
- __be32 acr_mask =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- ACR_PIPE_DEP |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- ACR_RPTCNT |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- ACR_APARK |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- ACR_PARKM |
-#endif
- 0;
- __be32 acr_val =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
-#endif
- 0;
- __be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
- SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- SPCR_TSEC2EP |
-#endif
- 0;
- __be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
- (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
- 0;
__be32 sccr_mask =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
SCCR_ENCCM |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
-#endif
- 0;
- __be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
- LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- LCRR_CLKDIV |
-#endif
- 0;
- __be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
- CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- CONFIG_SYS_LCRR_CLKDIV |
#endif
0;
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
&im->sysconf.sicrh);
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
-#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
}
#endif /* CONFIG_DISPLAY_AER_xxxx */
+#ifndef CONFIG_CPU_MPC83XX
/*
* Figure out the cause of the reset
*/
return 0;
}
+#endif