+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
#include <common.h>
+#include <asm-offsets.h>
#include <mpc83xx.h>
#include <ioports.h>
#include <asm/io.h>
+#include <asm/processor.h>
#ifdef CONFIG_USB_EHCI_FSL
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
#endif
+#include <linux/delay.h>
+
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
DECLARE_GLOBAL_DATA_PTR;
*/
void cpu_init_f (volatile immap_t * im)
{
- __be32 acr_mask =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- ACR_PIPE_DEP |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- ACR_RPTCNT |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- ACR_APARK |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- ACR_PARKM |
-#endif
- 0;
- __be32 acr_val =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
-#endif
- 0;
- __be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
- SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- SPCR_TSEC2EP |
-#endif
- 0;
- __be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
- (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
- 0;
__be32 sccr_mask =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
SCCR_ENCCM |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
-#endif
- 0;
- __be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
- LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- LCRR_CLKDIV |
-#endif
- 0;
- __be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
- CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- CONFIG_SYS_LCRR_CLKDIV |
#endif
0;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- /* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
+ /* global data region was cleared in start.S */
/* system performance tweaking */
clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
- gd->reset_status = __raw_readl(&im->reset.rsr);
+ gd->arch.reset_status = __raw_readl(&im->reset.rsr);
__raw_writel(~(RSR_RES), &im->reset.rsr);
/* AER - Arbiter Event Register - store status */
- gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
- gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
+ gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+ gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
/*
* RMR - Reset Mode Register
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
&im->sysconf.sicrh);
#ifdef CONFIG_SYS_SICRL
__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
+#ifdef CONFIG_SYS_GPR1
+ __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
-#ifdef CONFIG_USB_EHCI_FSL
-#ifndef CONFIG_MPC834x
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
uint32_t temp;
- struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+ struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
/* Configure interface. */
setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
-#endif
}
int cpu_init_r (void)
"reserved"
};
- int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
- >> AEATR_EVENT_SHIFT;
- int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
- >> AEATR_MSTR_ID_SHIFT;
- int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
- >> AEATR_TBST_SHIFT;
- int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
- >> AEATR_TSIZE_SHIFT;
- int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
- >> AEATR_TTYPE_SHIFT;
-
- if (!force && !gd->arbiter_event_address)
+ int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
+ >> AEATR_EVENT_SHIFT;
+ int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
+ >> AEATR_MSTR_ID_SHIFT;
+ int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
+ >> AEATR_TBST_SHIFT;
+ int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
+ >> AEATR_TSIZE_SHIFT;
+ int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
+ >> AEATR_TTYPE_SHIFT;
+
+ if (!force && !gd->arch.arbiter_event_address)
return 0;
puts("Arbiter Event Status:\n");
- printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
+ printf(" Event Address: 0x%08lX\n",
+ gd->arch.arbiter_event_address);
printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
- return gd->arbiter_event_address;
+ return gd->arch.arbiter_event_address;
}
#elif defined(CONFIG_DISPLAY_AER_BRIEF)
static int print_83xx_arb_event(int force)
{
- if (!force && !gd->arbiter_event_address)
+ if (!force && !gd->arch.arbiter_event_address)
return 0;
printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
- gd->arbiter_event_attributes, gd->arbiter_event_address);
+ gd->arch.arbiter_event_attributes,
+ gd->arch.arbiter_event_address);
- return gd->arbiter_event_address;
+ return gd->arch.arbiter_event_address;
}
#endif /* CONFIG_DISPLAY_AER_xxxx */
+#ifndef CONFIG_CPU_MPC83XX
/*
* Figure out the cause of the reset
*/
RSR_SRS, "External/Internal Soft"}, {
RSR_HRS, "External/Internal Hard"}
};
- static int n = sizeof bits / sizeof bits[0];
- ulong rsr = gd->reset_status;
+ static int n = ARRAY_SIZE(bits);
+ ulong rsr = gd->arch.reset_status;
int i;
char *sep;
return 0;
}
+#endif
projects / oweals / u-boot.git / blobdiff