*/
#include <common.h>
+#include <cpu_func.h>
+#include <irq_func.h>
+#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
#include <mpc83xx.h>
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
#include <linux/immap_qe.h>
#include <asm/io.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_CPU_MPC83XX
int checkcpu(void)
{
volatile immap_t *immr;
return 0;
}
+#endif
#ifndef CONFIG_SYSRESET
int
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
- msr &= ~( MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ msr = mfmsr();
+ msr &= ~(MSR_EE | MSR_IR | MSR_DR);
+ mtmsr(msr);
/* enable Reset Control Reg */
immap->reset.rpr = 0x52535445;
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ sync();
+ isync();
/* confirm Reset Control Reg is enabled */
- while(!((immap->reset.rcer) & RCER_CRE));
+ while(!((immap->reset.rcer) & RCER_CRE))
+ ;
udelay(200);
immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
+ msr = mfmsr();
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ mtmsr(msr);
/*
* Trying to execute the next instruction at a non-existing address
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*/
-
+#ifndef CONFIG_TIMER
unsigned long get_tbclk(void)
{
return (gd->bus_clk + 3L) / 4L;
}
-
+#endif
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
immr->wdt.swsrr = 0xaa39;
if (re_enable)
- enable_interrupts ();
+ enable_interrupts();
}
#endif
+#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
#endif
return 0;
}
+#endif /* !CONFIG_DM_ETH */
/*
* Initializes on-chip MMC controllers.
return 0;
#endif
}
+
+void ppcDWstore(unsigned int *addr, unsigned int *value)
+{
+ asm("lfd 1, 0(%1)\n\t"
+ "stfd 1, 0(%0)"
+ :
+ : "r" (addr), "r" (value)
+ : "memory");
+}
+
+void ppcDWload(unsigned int *addr, unsigned int *ret)
+{
+ asm("lfd 1, 0(%0)\n\t"
+ "stfd 1, 0(%1)"
+ :
+ : "r" (addr), "r" (ret)
+ : "memory");
+}