Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...
[oweals/u-boot.git] / arch / mips / mach-pic32 / cpu.c
index f2ee911df4d183059eec5d6103c07870370a3b39..1d8c39714411e34462bddc4c49fcdc035ad6e22d 100644 (file)
@@ -1,13 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015
  * Purna Chandra Mandal <purna.mandal@microchip.com>
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  */
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
+#include <init.h>
+#include <malloc.h>
 #include <mach/pic32.h>
 #include <mach/ddr.h>
 #include <dt-bindings/clock/microchip,clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static ulong clk_get_cpu_rate(void)
+static ulong rate(int id)
 {
        int ret;
        struct udevice *dev;
+       struct clk clk;
+       ulong rate;
 
        ret = uclass_get_device(UCLASS_CLK, 0, &dev);
        if (ret) {
-               panic("uclass-clk: device not found\n");
+               printf("clk-uclass not found\n");
                return 0;
        }
 
-       return clk_get_rate(dev);
+       clk.id = id;
+       ret = clk_request(dev, &clk);
+       if (ret < 0)
+               return ret;
+
+       rate = clk_get_rate(&clk);
+
+       clk_free(&clk);
+
+       return rate;
+}
+
+static ulong clk_get_cpu_rate(void)
+{
+       return rate(PB7CLK);
 }
 
 /* initialize prefetch module related to cpu_clk */
@@ -94,12 +111,14 @@ static void ddr2_pmd_ungate(void)
 }
 
 /* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
        ddr2_pmd_ungate();
        ddr2_phy_init();
        ddr2_ctrl_init();
-       return ddr2_calculate_size();
+       gd->ram_size = ddr2_calculate_size();
+
+       return 0;
 }
 
 int misc_init_r(void)
@@ -127,30 +146,25 @@ const char *get_core_name(void)
 }
 #endif
 #ifdef CONFIG_CMD_CLK
+
 int soc_clk_dump(void)
 {
-       int i, ret;
-       struct udevice *dev;
-
-       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
-       if (ret) {
-               printf("clk-uclass not found\n");
-               return ret;
-       }
+       int i;
 
        printf("PLL Speed: %lu MHz\n",
-              CLK_MHZ(clk_get_periph_rate(dev, PLLCLK)));
-       printf("CPU Speed: %lu MHz\n", CLK_MHZ(clk_get_rate(dev)));
-       printf("MPLL Speed: %lu MHz\n",
-              CLK_MHZ(clk_get_periph_rate(dev, MPLL)));
+              CLK_MHZ(rate(PLLCLK)));
+
+       printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
+
+       printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
 
        for (i = PB1CLK; i <= PB7CLK; i++)
                printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
-                      CLK_MHZ(clk_get_periph_rate(dev, i)));
+                      CLK_MHZ(rate(i)));
 
        for (i = REF1CLK; i <= REF5CLK; i++)
                printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
-                      CLK_MHZ(clk_get_periph_rate(dev, i)));
+                      CLK_MHZ(rate(i)));
        return 0;
 }
 #endif