Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / mips / mach-ath79 / ar934x / clk.c

diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9b41d3de60b615bb3a88f823d8bca1f76052791c..9fa2225ed2beb651db53eae771268465e9b6d507 100644 (file)
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -1,13 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
+#include <hang.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
 #include <asm/types.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 #include <mach/ar71xx_regs.h>
 #include <mach/ath79.h>
 #include <wait_bit.h>
@@ -90,7 +94,7 @@ static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
                setbits_be32(pll_reg_base + 0x8, BIT(30));
                udelay(5);
 
-               wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+               wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
 
                clrbits_be32(pll_reg_base + 0x8, BIT(30));
                udelay(5);
@@ -318,7 +322,8 @@ ulong get_ddr_freq(ulong dummy)
        return gd->mem_clk;
 }
 
-int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_ar934x_showclk(struct cmd_tbl *cmdtp, int flag, int argc,
+                     char *const argv[])
 {
        ar934x_update_clock();
        printf("CPU:       %8ld MHz\n", gd->cpu_clk / 1000000);