Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / mips / include / asm / mipsregs.h

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9ab506361e7897fb76ad0c8cdd37ebf3e58afc7a..7538e6b2e0bf62c608cdb1a3a74141cbfc42dee2 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
  * Copyright (C) 2000 Silicon Graphics, Inc.
@@ -5,8 +6,6 @@
  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  * Copyright (C) 2003, 2004  Maciej W. Rozycki
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 #ifndef _ASM_MIPSREGS_H
 #define _ASM_MIPSREGS_H
@@ -28,6 +27,7 @@
 #ifdef __ASSEMBLY__
 #define _ULCAST_
 #else
+#include <linux/bitops.h>
 #define _ULCAST_ (unsigned long)
 #endif
 
@@ -299,6 +299,7 @@
 #define         STATUSF_IP14           (_ULCAST_(1) <<  6)
 #define         STATUSB_IP15           7
 #define         STATUSF_IP15           (_ULCAST_(1) <<  7)
+#define ST0_IMPL               (_ULCAST_(3) <<  16)
 #define ST0_CH                 0x00040000
 #define ST0_NMI                        0x00080000
 #define ST0_SR                 0x00100000
@@ -1013,9 +1014,7 @@ do {                                                                      \
 #define __read_64bit_c0_split(source, sel)                             \
 ({                                                                     \
        unsigned long long __val;                                       \
-       unsigned long __flags;                                          \
                                                                        \
-       local_irq_save(__flags);                                        \
        if (sel == 0)                                                   \
                __asm__ __volatile__(                                   \
                        ".set\tmips64\n\t"                              \
@@ -1034,16 +1033,12 @@ do {                                                                    \
                        "dsra\t%L0, %L0, 32\n\t"                        \
                        ".set\tmips0"                                   \
                        : "=r" (__val));                                \
-       local_irq_restore(__flags);                                     \
                                                                        \
        __val;                                                          \
 })
 
 #define __write_64bit_c0_split(source, sel, val)                       \
 do {                                                                   \
-       unsigned long __flags;                                          \
-                                                                       \
-       local_irq_save(__flags);                                        \
        if (sel == 0)                                                   \
                __asm__ __volatile__(                                   \
                        ".set\tmips64\n\t"                              \
@@ -1064,7 +1059,6 @@ do {                                                                      \
                        "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
                        ".set\tmips0"                                   \
                        : : "r" (val));                                 \
-       local_irq_restore(__flags);                                     \
 } while (0)
 
 #define __readx_32bit_c0_register(source)                              \
@@ -2005,6 +1999,17 @@ static inline unsigned int get_ebase_cpunum(void)
        return read_c0_ebase() & 0x3ff;
 }
 
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+                                u32 low1)
+{
+       write_c0_entrylo0(low0);
+       write_c0_pagemask(pagemask);
+       write_c0_entrylo1(low1);
+       write_c0_entryhi(hi);
+       write_c0_index(index);
+       tlb_write_indexed();
+}
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_MIPSREGS_H */