MIPS: add compile time definition of L2 cache size

[oweals/u-boot.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e3e79455679912361d8ff9722928dddcb57b385c..f5d81b822c48d5500cf805a3ae7e8c311737f379 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -408,9 +408,17 @@ config SYS_ICACHE_LINE_SIZE
        help
          The size of L1 Icache lines, if known at compile time.
 
+config SYS_SCACHE_LINE_SIZE
+       int
+       default 0
+       help
+         The size of L2 cache lines, if known at compile time.
+
+
 config SYS_CACHE_SIZE_AUTO
        def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
-               SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
+               SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
+               SYS_SCACHE_LINE_SIZE = 0
        help
          Select this (or let it be auto-selected by not defining any cache
          sizes) in order to allow U-Boot to automatically detect the sizes