Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-uniphier / clk / clk-ld11.c

diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
index 36aa7879846ef0c0b08bf6268f71ec6cb8cab69e..d241a65382f67a486c7d4602e771cc81ababbe84 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -1,12 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Socionext Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include <common.h>
 #include <spl.h>
 #include <linux/bitops.h>
+#include <linux/delay.h>
 #include <linux/io.h>
 
 #include "../init.h"
@@ -18,33 +17,27 @@
 void uniphier_ld11_clk_init(void)
 {
        /* if booted from a device other than USB, without stand-by MPU */
-       if ((readl(SG_PINMON0) & BIT(27)) &&
+       if ((readl(sg_base + SG_PINMON0) & BIT(27)) &&
            uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
-               writel(1, SG_ETPHYPSHUT);
-               writel(1, SG_ETPHYCNT);
+               writel(1, sg_base + SG_ETPHYPSHUT);
+               writel(1, sg_base + SG_ETPHYCNT);
 
                udelay(1); /* wait for regulator level 1.1V -> 2.5V */
 
-               writel(3, SG_ETPHYCNT);
-               writel(3, SG_ETPHYPSHUT);
-               writel(7, SG_ETPHYCNT);
+               writel(3, sg_base + SG_ETPHYCNT);
+               writel(3, sg_base + SG_ETPHYPSHUT);
+               writel(7, sg_base + SG_ETPHYCNT);
        }
 
        /* TODO: use "mmc-pwrseq-emmc" */
        writel(1, SDCTRL_EMMC_HW_RESET);
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
        {
-               /* FIXME: the current clk driver can not handle parents */
-               u32 tmp;
                int ch;
 
-               tmp = readl(SC_CLKCTRL4);
-               tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
-               writel(tmp, SC_CLKCTRL4);
-
                for (ch = 0; ch < 3; ch++) {
-                       void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL;
+                       void __iomem *phyctrl = sg_base + SG_USBPHYCTRL;
 
                        writel(0x82280600, phyctrl + 8 * ch);
                        writel(0x00000106, phyctrl + 8 * ch + 4);