Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-tegra / tegra30 / clock.c

diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 4fd8b8a3b1fb69a15157ee80c88283d6455d9cd8..b0641c6a41a41c4951a5bfd4a885a8bdd8a092bd 100644 (file)
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -1,14 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 /* Tegra30 Clock control functions */
 
 #include <common.h>
 #include <errno.h>
+#include <init.h>
+#include <log.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
@@ -16,6 +17,7 @@
 #include <asm/arch-tegra/timer.h>
 #include <div64.h>
 #include <fdtdec.h>
+#include <linux/delay.h>
 
 /*
  * Clock types that we can use as a source. The Tegra30 has muxes for the
@@ -696,7 +698,7 @@ static int tegra_plle_train(void)
        } while (--timeout);
 
        if (timeout == 0) {
-               error("timeout waiting for PLLE to become ready");
+               pr_err("timeout waiting for PLLE to become ready");
                return -ETIMEDOUT;
        }
 
@@ -726,7 +728,7 @@ int tegra_plle_enable(void)
        if ((value & PLLE_MISC_PLL_READY) == 0) {
                err = tegra_plle_train();
                if (err < 0) {
-                       error("failed to train PLLE: %d", err);
+                       pr_err("failed to train PLLE: %d", err);
                        return err;
                }
        }
@@ -772,7 +774,7 @@ int tegra_plle_enable(void)
        } while (--timeout);
 
        if (timeout == 0) {
-               error("timeout waiting for PLLE to lock");
+               pr_err("timeout waiting for PLLE to lock");
                return -ETIMEDOUT;
        }