+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
#include <errno.h>
+#include <linux/delay.h>
#include <asm/io.h>
#include <asm/types.h>
-#include <asm/arch/flow.h>
+
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
#define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8)
u32 value, mask = state ? (1 << id) : 0, old_mask;
unsigned long start, timeout = 25;
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ value = tegra_pmc_readl(PWRGATE_STATUS);
old_mask = value & (1 << id);
if (mask == old_mask)
return 0;
- writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
+ tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
start = get_timer(0);
while (get_timer(start) < timeout) {
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ value = tegra_pmc_readl(PWRGATE_STATUS);
if ((value & (1 << id)) == mask)
return 0;
}
else
value = 1 << id;
- writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
+ tegra_pmc_writel(value, REMOVE_CLAMPING);
return 0;
}
-static void tegra_powergate_ram_repair(void)
-{
-#ifdef CONFIG_TEGRA124
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
- /* Request RAM repair for cluster 0 and wait until complete */
- setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
- ;
-
- /* Same for cluster 1 */
- setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
- ;
-#endif
-}
-
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
- tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);