common: Move ARM cache operations out of common.h

[oweals/u-boot.git] / arch / arm / mach-tegra / ivc.c

diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c
index cf6626fb12c7d60983ca8600d9d7e865c8a123f9..a448f2df30289b1d400dd20cc4067b0591b096f0 100644 (file)
--- a/arch/arm/mach-tegra/ivc.c
+++ b/arch/arm/mach-tegra/ivc.c
@@ -1,10 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <asm/io.h>
 #include <asm/arch-tegra/ivc.h>
 
@@ -493,7 +493,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
               (TEGRA_IVC_ALIGN - 1));
 
        if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) {
-               error("tegra_ivc: nframes * frame_size overflows\n");
+               pr_err("tegra_ivc: nframes * frame_size overflows\n");
                return -EINVAL;
        }
 
@@ -503,12 +503,12 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
         */
        if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) ||
            (qbase2 & (TEGRA_IVC_ALIGN - 1))) {
-               error("tegra_ivc: channel start not aligned\n");
+               pr_err("tegra_ivc: channel start not aligned\n");
                return -EINVAL;
        }
 
        if (frame_size & (TEGRA_IVC_ALIGN - 1)) {
-               error("tegra_ivc: frame size not adequately aligned\n");
+               pr_err("tegra_ivc: frame size not adequately aligned\n");
                return -EINVAL;
        }
 
@@ -521,7 +521,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
        }
 
        if (ret) {
-               error("tegra_ivc: queue regions overlap\n");
+               pr_err("tegra_ivc: queue regions overlap\n");
                return ret;
        }