Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-socfpga / spl_gen5.c

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index ccdc661d05a93158d7db8026a6b5fb5eee15dd0f..5a7c5ef76d5d097873fa1bc8c7e16e86c099febe 100644 (file)
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -4,6 +4,9 @@
  */
 
 #include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
 #include <asm/io.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
@@ -20,31 +23,27 @@
 #include <debug_uart.h>
 #include <fdtdec.h>
 #include <watchdog.h>
+#include <dm/uclass.h>
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_system_manager *sysmgr_regs =
-       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 u32 spl_boot_device(void)
 {
-       const u32 bsel = readl(&sysmgr_regs->bootinfo);
+       const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+                              SYSMGR_GEN5_BOOTINFO);
 
        switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
        case 0x1:       /* FPGA (HPS2FPGA Bridge) */
                return BOOT_DEVICE_RAM;
        case 0x2:       /* NAND Flash (1.8V) */
        case 0x3:       /* NAND Flash (3.0V) */
-               socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
                return BOOT_DEVICE_NAND;
        case 0x4:       /* SD/MMC External Transceiver (1.8V) */
        case 0x5:       /* SD/MMC Internal Transceiver (3.0V) */
-               socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
-               socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
                return BOOT_DEVICE_MMC1;
        case 0x6:       /* QSPI Flash (1.8V) */
        case 0x7:       /* QSPI Flash (3.0V) */
-               socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
                return BOOT_DEVICE_SPI;
        default:
                printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -53,9 +52,9 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(const u32 boot_device)
 {
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
        return MMCSD_MODE_FS;
 #else
        return MMCSD_MODE_RAW;
@@ -66,25 +65,30 @@ u32 spl_boot_mode(const u32 boot_device)
 void board_init_f(ulong dummy)
 {
        const struct cm_config *cm_default_cfg = cm_get_default_config();
-       unsigned long sdram_size;
        unsigned long reg;
        int ret;
+       struct udevice *dev;
+
+       ret = spl_early_init();
+       if (ret)
+               hang();
+
+       socfpga_get_managers_addr();
 
        /*
-        * First C code to run. Clear fake OCRAM ECC first as SBE
+        * Clear fake OCRAM ECC first as SBE
         * and DBE might triggered during power on
         */
-       reg = readl(&sysmgr_regs->eccgrp_ocram);
+       reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
        if (reg & SYSMGR_ECC_OCRAM_SERR)
                writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
-                      &sysmgr_regs->eccgrp_ocram);
+                      socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
        if (reg & SYSMGR_ECC_OCRAM_DERR)
                writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
-                      &sysmgr_regs->eccgrp_ocram);
-
-       memset(__bss_start, 0, __bss_end - __bss_start);
+                      socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 
        socfpga_sdram_remap_zero();
+       socfpga_pl310_clear();
 
        debug("Freezing all I/O banks\n");
        /* freeze all IO banks */
@@ -98,10 +102,7 @@ void board_init_f(ulong dummy)
                socfpga_bridges_reset(1);
        }
 
-       socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-       socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
        socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-
        timer_init();
 
        debug("Reconfigure Clock Manager\n");
@@ -123,9 +124,8 @@ void board_init_f(ulong dummy)
        sysmgr_pinmux_init();
        sysmgr_config_warmrstcfgio(0);
 
-       /* De-assert reset for peripherals and bridges based on handoff */
-       reset_deassert_peripherals_handoff();
-       socfpga_bridges_reset(0);
+       /* Set bridges handoff value */
+       socfpga_bridges_set_handoff_regs(true, true, true);
 
        debug("Unfreezing/Thaw all I/O banks\n");
        /* unfreeze / thaw all IO banks */
@@ -136,36 +136,20 @@ void board_init_f(ulong dummy)
        debug_uart_init();
 #endif
 
-       ret = spl_early_init();
-       if (ret) {
-               debug("spl_early_init() failed: %d\n", ret);
-               hang();
-       }
+       ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+       if (ret)
+               debug("Reset init failed: %d\n", ret);
+
+#ifdef CONFIG_SPL_NAND_DENALI
+       clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
+#endif
 
        /* enable console uart printing */
        preloader_console_init();
 
-       if (sdram_mmr_init_full(0xffffffff) != 0) {
-               puts("SDRAM init failed.\n");
-               hang();
-       }
-
-       debug("SDRAM: Calibrating PHY\n");
-       /* SDRAM calibration */
-       if (sdram_calibration_full() == 0) {
-               puts("SDRAM calibration failed.\n");
-               hang();
-       }
-
-       sdram_size = sdram_calculate_size();
-       debug("SDRAM: %ld MiB\n", sdram_size >> 20);
-
-       /* Sanity check ensure correct SDRAM size specified */
-       if (get_ram_size(0, sdram_size) != sdram_size) {
-               puts("SDRAM size check failed!\n");
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret) {
+               debug("DRAM init failed: %d\n", ret);
                hang();
        }
-
-       if (!socfpga_is_booting_from_fpga())
-               socfpga_bridges_reset(1);
 }