*/
#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <fdtdec.h>
#include <watchdog.h>
#include <dm/uclass.h>
+#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
u32 spl_boot_device(void)
{
- const u32 bsel = readl(&sysmgr_regs->bootinfo);
+ const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_GEN5_BOOTINFO);
switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
case 0x1: /* FPGA (HPS2FPGA Bridge) */
}
#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
* Clear fake OCRAM ECC first as SBE
* and DBE might triggered during power on
*/
- reg = readl(&sysmgr_regs->eccgrp_ocram);
+ reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
if (reg & SYSMGR_ECC_OCRAM_SERR)
writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
- &sysmgr_regs->eccgrp_ocram);
+ socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
if (reg & SYSMGR_ECC_OCRAM_DERR)
writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
- &sysmgr_regs->eccgrp_ocram);
+ socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
socfpga_sdram_remap_zero();
socfpga_pl310_clear();
debug("Reset init failed: %d\n", ret);
#ifdef CONFIG_SPL_NAND_DENALI
- struct socfpga_reset_manager *reset_manager_base =
- (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-
- clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4));
+ clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
#endif
/* enable console uart printing */