Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-socfpga / spl_gen5.c

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 47e63709ad88dabd132cc0b94ab42d151ebfdf9b..5a7c5ef76d5d097873fa1bc8c7e16e86c099febe 100644 (file)
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -4,6 +4,9 @@
  */
 
 #include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
 #include <asm/io.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
@@ -21,15 +24,14 @@
 #include <fdtdec.h>
 #include <watchdog.h>
 #include <dm/uclass.h>
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_system_manager *sysmgr_regs =
-       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 u32 spl_boot_device(void)
 {
-       const u32 bsel = readl(&sysmgr_regs->bootinfo);
+       const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+                              SYSMGR_GEN5_BOOTINFO);
 
        switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
        case 0x1:       /* FPGA (HPS2FPGA Bridge) */
@@ -50,7 +52,7 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(const u32 boot_device)
 {
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
        return MMCSD_MODE_FS;
@@ -67,17 +69,23 @@ void board_init_f(ulong dummy)
        int ret;
        struct udevice *dev;
 
+       ret = spl_early_init();
+       if (ret)
+               hang();
+
+       socfpga_get_managers_addr();
+
        /*
-        * First C code to run. Clear fake OCRAM ECC first as SBE
+        * Clear fake OCRAM ECC first as SBE
         * and DBE might triggered during power on
         */
-       reg = readl(&sysmgr_regs->eccgrp_ocram);
+       reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
        if (reg & SYSMGR_ECC_OCRAM_SERR)
                writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
-                      &sysmgr_regs->eccgrp_ocram);
+                      socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
        if (reg & SYSMGR_ECC_OCRAM_DERR)
                writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
-                      &sysmgr_regs->eccgrp_ocram);
+                      socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 
        socfpga_sdram_remap_zero();
        socfpga_pl310_clear();
@@ -128,16 +136,14 @@ void board_init_f(ulong dummy)
        debug_uart_init();
 #endif
 
-       ret = spl_early_init();
-       if (ret) {
-               debug("spl_early_init() failed: %d\n", ret);
-               hang();
-       }
-
        ret = uclass_get_device(UCLASS_RESET, 0, &dev);
        if (ret)
                debug("Reset init failed: %d\n", ret);
 
+#ifdef CONFIG_SPL_NAND_DENALI
+       clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
+#endif
+
        /* enable console uart printing */
        preloader_console_init();