Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-socfpga / spl_a10.c

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb424f23f5fecf18f88ec2d97f62c3dbc06..45aea4ab6cc3b90e9f2fe0170001def4593b0b2c 100644 (file)
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -1,9 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
 #include <asm/io.h>
 #include <asm/pl310.h>
 #include <asm/u-boot.h>
@@ -23,15 +26,49 @@
 #include <fdtdec.h>
 #include <watchdog.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/fpga_manager.h>
+#include <mmc.h>
+#include <memalign.h>
+
+#define FPGA_BUFSIZ    16 * 1024
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_system_manager *sysmgr_regs =
-       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#define BOOTROM_SHARED_MEM_SIZE                0x800   /* 2KB */
+#define BOOTROM_SHARED_MEM_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        SOCFPGA_PHYS_OCRAM_SIZE - \
+                                        BOOTROM_SHARED_MEM_SIZE)
+#define RST_STATUS_SHARED_ADDR         (BOOTROM_SHARED_MEM_ADDR + 0x438)
+static u32 rst_mgr_status __section(.data);
+
+/*
+ * Bootrom will clear the status register in reset manager and stores the
+ * reset status value in shared memory. Bootrom stores shared data at last
+ * 2KB of onchip RAM.
+ * This function save reset status provided by BootROM to rst_mgr_status.
+ * More information about reset status register value can be found in reset
+ * manager register description.
+ * When running in debugger without Bootrom, r0 to r3 are random values.
+ * So, skip save the value when r0 is not BootROM shared data address.
+ *
+ * r0 - Contains the pointer to the shared memory block. The shared
+ *     memory block is located in the top 2 KB of on-chip RAM.
+ * r1 - contains the length of the shared memory.
+ * r2 - unused and set to 0x0.
+ * r3 - points to the version block.
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+                     unsigned long r3)
+{
+       if (r0 == BOOTROM_SHARED_MEM_ADDR)
+               rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
+
+       save_boot_params_ret();
+}
 
 u32 spl_boot_device(void)
 {
-       const u32 bsel = readl(&sysmgr_regs->bootinfo);
+       const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
 
        switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
        case 0x1:       /* FPGA (HPS2FPGA Bridge) */
@@ -56,7 +93,7 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(const u32 boot_device)
 {
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
        return MMCSD_MODE_FS;
@@ -68,24 +105,54 @@ u32 spl_boot_mode(const u32 boot_device)
 
 void spl_board_init(void)
 {
+       ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
        /* enable console uart printing */
        preloader_console_init();
        WATCHDOG_RESET();
 
        arch_early_init_r();
+
+       /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+       if (is_fpgamgr_user_mode()) {
+               int ret = config_pins(gd->fdt_blob, "shared");
+
+               if (ret)
+                       return;
+
+               ret = config_pins(gd->fdt_blob, "fpga");
+               if (ret)
+                       return;
+       } else if (!is_fpgamgr_early_user_mode()) {
+               /* Program IOSSM(early IO release) or full FPGA */
+               fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+       }
+
+       /* If the IOSSM/full FPGA is already loaded, start DDR */
+       if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+               ddr_calibration_sequence();
+
+       if (!is_fpgamgr_user_mode())
+               fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 }
 
 void board_init_f(ulong dummy)
 {
+       if (spl_early_init())
+               hang();
+
+       socfpga_get_managers_addr();
+
+       dcache_disable();
+
        socfpga_init_security_policies();
        socfpga_sdram_remap_zero();
+       socfpga_pl310_clear();
 
        /* Assert reset to all except L4WD0 and L4TIMER0 */
        socfpga_per_reset_all();
        socfpga_watchdog_disable();
 
-       spl_early_init();
-
        /* Configure the clock based on handoff */
        cm_basic_init(gd->fdt_blob);