*/
#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
#include <asm/io.h>
#include <asm/pl310.h>
#include <asm/u-boot.h>
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
+#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ SOCFPGA_PHYS_OCRAM_SIZE - \
+ BOOTROM_SHARED_MEM_SIZE)
+#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
+static u32 rst_mgr_status __section(.data);
+
+/*
+ * Bootrom will clear the status register in reset manager and stores the
+ * reset status value in shared memory. Bootrom stores shared data at last
+ * 2KB of onchip RAM.
+ * This function save reset status provided by BootROM to rst_mgr_status.
+ * More information about reset status register value can be found in reset
+ * manager register description.
+ * When running in debugger without Bootrom, r0 to r3 are random values.
+ * So, skip save the value when r0 is not BootROM shared data address.
+ *
+ * r0 - Contains the pointer to the shared memory block. The shared
+ * memory block is located in the top 2 KB of on-chip RAM.
+ * r1 - contains the length of the shared memory.
+ * r2 - unused and set to 0x0.
+ * r3 - points to the version block.
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
+{
+ if (r0 == BOOTROM_SHARED_MEM_ADDR)
+ rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
+
+ save_boot_params_ret();
+}
u32 spl_boot_device(void)
{
- const u32 bsel = readl(&sysmgr_regs->bootinfo);
+ const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
case 0x1: /* FPGA (HPS2FPGA Bridge) */
}
#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;
void board_init_f(ulong dummy)
{
+ if (spl_early_init())
+ hang();
+
+ socfpga_get_managers_addr();
+
dcache_disable();
socfpga_init_security_policies();
socfpga_sdram_remap_zero();
+ socfpga_pl310_clear();
/* Assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
socfpga_watchdog_disable();
- spl_early_init();
-
/* Configure the clock based on handoff */
cm_basic_init(gd->fdt_blob);