Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-socfpga / misc_arria10.c

diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index f347ae857e036bee4475f39509a6e9e4cb7861f5..bf978053ca6443da898558cbf020e0a91120e514 100644 (file)
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <init.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <ns16550.h>
@@ -28,8 +29,26 @@
 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7  0x78
 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3  0x98
 
-static struct socfpga_system_manager *sysmgr_regs =
-       (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+/*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+       {
+               /* Family */
+               Altera_SoCFPGA,
+               /* Interface type */
+               fast_passive_parallel,
+               /* No limitation as additional data will be ignored */
+               -1,
+               /* No device function table */
+               NULL,
+               /* Base interface address specified in driver */
+               NULL,
+               /* No cookie implementation */
+               0
+       },
+};
+
 #if defined(CONFIG_SPL_BUILD)
 static struct pl310_regs *const pl310 =
        (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -60,7 +79,8 @@ void socfpga_init_security_policies(void)
        writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
        writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
 
-       writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
+       writel(0x0007FFFF,
+              socfpga_get_sysmgr_addr() + SYSMGR_A10_ECC_INTMASK_SET);
 }
 
 void socfpga_sdram_remap_zero(void)
@@ -73,7 +93,7 @@ void socfpga_sdram_remap_zero(void)
 int arch_early_init_r(void)
 {
        /* Add device descriptor to FPGA device table */
-       socfpga_fpga_add();
+       socfpga_fpga_add(&altera_fpga[0]);
 
        return 0;
 }
@@ -84,8 +104,9 @@ int arch_early_init_r(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-       const u32 bsel =
-               SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
+       const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
+                                  SYSMGR_A10_BOOTINFO);
+       const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
 
        puts("CPU:   Altera SoCFPGA Arria 10\n");
 
@@ -94,7 +115,7 @@ int print_cpuinfo(void)
 }
 #endif
 
-void do_bridge_reset(int enable)
+void do_bridge_reset(int enable, unsigned int mask)
 {
        if (enable)
                socfpga_reset_deassert_bridges_handoff();