Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-socfpga / clock_manager.c

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index bc2c0f8854ab8fa409df306c31b74e7e2ad8784a..a4a97b6a0fcf48cfb11a51d196c89e1fa408201c 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -4,24 +4,25 @@
  */
 
 #include <common.h>
+#include <command.h>
+#include <init.h>
 #include <wait_bit.h>
 #include <asm/io.h>
 #include <asm/arch/clock_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 void cm_wait_for_lock(u32 mask)
 {
        u32 inter_val;
        u32 retry = 0;
        do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-               inter_val = readl(&clock_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-               inter_val = readl(&clock_manager_base->stat) & mask;
+               inter_val = readl(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_INTER) & mask;
+#else
+               inter_val = readl(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_STAT) & mask;
 #endif
                /* Wait for stable lock */
                if (inter_val == mask)
@@ -36,22 +37,25 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-       return wait_for_bit_le32(&clock_manager_base->stat,
-                                CLKMGR_STAT_BUSY, false, 20000, false);
+       return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
+                                CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
+                                false);
 }
 
 int set_cpu_clk_info(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
        /* Calculate the clock frequencies required for drivers */
        cm_get_l4_sp_clk_hz();
        cm_get_mmc_controller_clk_hz();
+#endif
 
        gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
        gd->bd->bi_dsp_freq = 0;
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
        gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
        gd->bd->bi_ddr_freq = 0;
 #endif
 
@@ -59,7 +63,8 @@ int set_cpu_clk_info(void)
 }
 
 #ifndef CONFIG_SPL_BUILD
-static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
+                        char *const argv[])
 {
        cm_print_clock_quick_summary();
        return 0;