Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-snapdragon / pinctrl-snapdragon.c

diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index 5365ccdb70c64b05b8fc0c79b05b0cb23526b384..442d236255011f8d88d6b641990012221730fe8e 100644 (file)
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -11,6 +11,7 @@
 #include <errno.h>
 #include <asm/io.h>
 #include <dm/pinctrl.h>
+#include <linux/bitops.h>
 #include "pinctrl-snapdragon.h"
 
 struct msm_pinctrl_priv {
@@ -22,7 +23,7 @@ struct msm_pinctrl_priv {
 #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
 #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
 #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_ENABLE BIT(9)
+#define TLMM_GPIO_DISABLE BIT(9)
 
 static const struct pinconf_param msm_conf_params[] = {
        { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
@@ -74,7 +75,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
        struct msm_pinctrl_priv *priv = dev_get_priv(dev);
 
        clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-                       TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
+                       TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
                        priv->data->get_function_mux(func_selector) << 2);
        return 0;
 }
@@ -113,8 +114,8 @@ static struct pinctrl_ops msm_pinctrl_ops = {
 };
 
 static const struct udevice_id msm_pinctrl_ids[] = {
-       { .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data },
        { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
+       { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
        { }
 };