mach-snapdragon: Fix UART clock flow

[oweals/u-boot.git] / arch / arm / mach-snapdragon / clock-snapdragon.h

diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h
index 2cff4f8a06c279ad6369662d73232868b94ddc9e..58fab40a2e4530abba059ebc1f27e4f9ab0c5d34 100644 (file)
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
@@ -11,13 +11,18 @@
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
 #define CFG_CLK_SRC_MASK  (7 << 8)
 
-struct gpll0_ctrl {
+struct pll_vote_clk {
        uintptr_t status;
        int status_bit;
        uintptr_t ena_vote;
        int vote_bit;
 };
 
+struct vote_clk {
+       uintptr_t cbcr_reg;
+       uintptr_t ena_vote;
+       int vote_bit;
+};
 struct bcr_regs {
        uintptr_t cfg_rcgr;
        uintptr_t cmd_rcgr;
@@ -30,9 +35,10 @@ struct msm_clk_priv {
        phys_addr_t base;
 };
 
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
 void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
 void clk_enable_cbc(phys_addr_t cbcr);
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
                          int div, int m, int n, int source);