Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-rockchip / rk3368 / rk3368.c

diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index 1ed06c5352a07ebcbb3359249bd1840722b0e063..1c6d65a588700986e2b705c0468caa2a5245fdd1 100644 (file)
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -5,12 +5,17 @@
  */
 
 #include <common.h>
+#include <init.h>
+#include <syscon.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/cru_rk3368.h>
 #include <asm/arch-rockchip/grf_rk3368.h>
-#include <syscon.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,16 +56,10 @@ static struct mm_region rk3368_mem_map[] = {
 
 struct mm_region *mem_map = rk3368_mem_map;
 
-int dram_init_banksize(void)
-{
-       size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
-       /* Reserve 0x200000 for ATF bl31 */
-       gd->bd->bi_dram[0].start = 0x200000;
-       gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
-       return 0;
-}
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+       [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
+       [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
+};
 
 #ifdef CONFIG_ARCH_EARLY_INIT_R
 static int mcu_init(void)
@@ -97,6 +96,78 @@ int arch_early_init_r(void)
 }
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * The SPL (and also the full U-Boot stage on the RK3368) will run in
+ * secure mode (i.e. EL3) and an ATF will eventually be booted before
+ * starting up the operating system... so we can initialize the SGRF
+ * here and rely on the ATF installing the final (secure) policy
+ * later.
+ */
+static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
+{
+       const uintptr_t SGRF_BASE =
+               (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+
+       return SGRF_BASE + sizeof(u32) * no;
+}
+
+static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
+{
+       const uintptr_t SGRF_BASE =
+               (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+       const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
+       const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
+
+       return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
+}
+
+static void sgrf_init(void)
+{
+       struct rk3368_cru * const cru =
+               (struct rk3368_cru * const)rockchip_get_cru();
+       const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
+       const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
+       const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
+
+       /* Set all configurable IP to 'non secure'-mode */
+       rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
+       rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
+       rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
+
+       /*
+        * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
+        * Original comment: "ddr space set no secure mode"
+        */
+       rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
+       rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
+       rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
+
+       /* Set 'secure dma' to 'non secure'-mode */
+       rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
+       rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
+
+       dsb();  /* barrier */
+
+       rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+       rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+
+       dsb();  /* barrier */
+       udelay(10);
+
+       rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+       rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+}
+
+int arch_cpu_init(void)
+{
+       /* Reset security, so we can use DMA in the MMC drivers */
+       sgrf_init();
+
+       return 0;
+}
+#endif
+
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
 {
@@ -124,6 +195,46 @@ void board_debug_uart_init(void)
                     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
        rk_clrsetreg(&grf->gpio2d_iomux,
                     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
+       struct rk3368_pmu_grf * const pmugrf __maybe_unused =
+               (struct rk3368_pmu_grf * const)0xff738000;
+
+       enum {
+               /* UART4 */
+               GPIO0D2_MASK            = GENMASK(5, 4),
+               GPIO0D2_GPIO            = 0,
+               GPIO0D2_UART4_SOUT      = (3 << 4),
+
+               GPIO0D3_MASK            = GENMASK(7, 6),
+               GPIO0D3_GPIO            = 0,
+               GPIO0D3_UART4_SIN       = (3 << 6),
+       };
+
+       /* Enable early UART4 on the PX5 */
+       rk_clrsetreg(&pmugrf->gpio0d_iomux,
+                    GPIO0D2_MASK | GPIO0D3_MASK,
+                    GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
+       struct rk3368_grf * const grf =
+               (struct rk3368_grf * const)0xff770000;
+
+       enum {
+               GPIO2A6_SHIFT           = 12,
+               GPIO2A6_MASK            = GENMASK(13, 12),
+               GPIO2A6_GPIO            = 0,
+               GPIO2A6_UART2_SIN       = (2 << GPIO2A6_SHIFT),
+
+               GPIO2A5_SHIFT           = 10,
+               GPIO2A5_MASK            = GENMASK(11, 10),
+               GPIO2A5_GPIO            = 0,
+               GPIO2A5_UART2_SOUT      = (2 << GPIO2A5_SHIFT),
+       };
+
+       /* Enable early UART2 on the RK3368 */
+       rk_clrsetreg(&grf->gpio2a_iomux,
+                    GPIO2A6_MASK, GPIO2A6_UART2_SIN);
+       rk_clrsetreg(&grf->gpio2a_iomux,
+                    GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
 #endif
 }
 #endif