Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-mvebu / include / mach / soc.h

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index b31794036691e4f6e0f6aa7e071682c02b5c8c65..3f3b15aa8ab6a00bb83da88d50b73ae3d57a0605 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -1,39 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2009
  * Marvell Semiconductor <www.marvell.com>
  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  *
  * Header file for the Marvell's Feroceon CPU core.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _MVEBU_SOC_H
 #define _MVEBU_SOC_H
 
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
 #define SOC_MV78230_ID         0x7823
 #define SOC_MV78260_ID         0x7826
 #define SOC_MV78460_ID         0x7846
+#define SOC_88F6720_ID         0x6720
 #define SOC_88F6810_ID         0x6810
 #define SOC_88F6820_ID         0x6820
 #define SOC_88F6828_ID         0x6828
+#define SOC_98DX3236_ID                0xf410
+#define SOC_98DX3336_ID                0xf400
+#define SOC_98DX4251_ID                0xfc00
+
+/* A375 revisions */
+#define MV_88F67XX_A0_ID       0x3
 
 /* A38x revisions */
 #define MV_88F68XX_Z1_ID       0x0
 #define MV_88F68XX_A0_ID       0x4
+#define MV_88F68XX_B0_ID       0xa
 
 /* TCLK Core Clock definition */
 #ifndef CONFIG_SYS_TCLK
 #define CONFIG_SYS_TCLK                250000000       /* 250MHz */
 #endif
 
-/* Armada XP PLL frequency (used for NAND clock generation) */
-#define CONFIG_SYS_MVEBU_PLL_CLOCK     2000000000
-
 /* SOC specific definations */
 #define INTREG_BASE            0xd0000000
 #define INTREG_BASE_ADDR_REG   (INTREG_BASE + 0x20080)
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
 /*
  * The SPL U-Boot version still runs with the default
  * address for the internal registers, configured by
@@ -42,6 +50,8 @@
  * required for the Linux kernel.
  */
 #define SOC_REGS_PHY_BASE      0xd0000000
+#elif defined(CONFIG_ARMADA_8K)
+#define SOC_REGS_PHY_BASE      0xf0000000
 #else
 #define SOC_REGS_PHY_BASE      0xf1000000
 #endif
@@ -51,6 +61,7 @@
 #define MVEBU_L2_CACHE_BASE    (MVEBU_REGISTER(0x08000))
 #define CONFIG_SYS_PL310_BASE  MVEBU_L2_CACHE_BASE
 #define MVEBU_TWSI_BASE                (MVEBU_REGISTER(0x11000))
+#define MVEBU_TWSI1_BASE       (MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE         (MVEBU_REGISTER(0x18000))
 #define MVEBU_GPIO0_BASE       (MVEBU_REGISTER(0x18100))
 #define MVEBU_GPIO1_BASE       (MVEBU_REGISTER(0x18140))
@@ -63,11 +74,17 @@
 #define MVEBU_REG_PCIE_BASE    (MVEBU_REGISTER(0x40000))
 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
 #define MVEBU_USB20_BASE       (MVEBU_REGISTER(0x58000))
+#define MVEBU_REG_PCIE0_BASE   (MVEBU_REGISTER(0x80000))
 #define MVEBU_AXP_SATA_BASE    (MVEBU_REGISTER(0xa0000))
 #define MVEBU_SATA0_BASE       (MVEBU_REGISTER(0xa8000))
 #define MVEBU_NAND_BASE                (MVEBU_REGISTER(0xd0000))
 #define MVEBU_SDIO_BASE                (MVEBU_REGISTER(0xd8000))
 #define MVEBU_LCD_BASE         (MVEBU_REGISTER(0xe0000))
+#ifdef CONFIG_ARMADA_MSYS
+#define MVEBU_DFX_BASE         (MBUS_DFX_BASE)
+#else
+#define MVEBU_DFX_BASE         (MVEBU_REGISTER(0xe4000))
+#endif
 
 #define SOC_COHERENCY_FABRIC_CTRL_REG  (MVEBU_REGISTER(0x20200))
 #define MBUS_ERR_PROP_EN       (1 << 8)
@@ -87,8 +104,20 @@
 #define SPI_PUP_EN             BIT(5)
 
 #define MVEBU_CORE_DIV_CLK_CTRL(i)     (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#ifdef CONFIG_ARMADA_MSYS
+#define MVEBU_DFX_DIV_CLK_CTRL(i)      (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
+#define NAND_ECC_DIVCKL_RATIO_OFFS     6
+#define NAND_ECC_DIVCKL_RATIO_MASK     (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
+#define MVEBU_DFX_DIV_CLK_CTRL(i)      (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
+#endif
+#ifdef CONFIG_ARMADA_MSYS
+#define NAND_ECC_DIVCKL_RATIO_OFFS     6
+#define NAND_ECC_DIVCKL_RATIO_MASK     (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
 #define NAND_ECC_DIVCKL_RATIO_OFFS     8
 #define NAND_ECC_DIVCKL_RATIO_MASK     (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
+#endif
 
 #define SDRAM_MAX_CS           4
 #define SDRAM_ADDR_MASK                0xFF000000
@@ -105,8 +134,23 @@
 #define BOOTROM_ERR_MODE_OFFS  28
 #define BOOTROM_ERR_MODE_MASK  (0xf << BOOTROM_ERR_MODE_OFFS)
 #define BOOTROM_ERR_MODE_UART  0x6
+#define BOOTROM_ERR_CODE_OFFS  0
+#define BOOTROM_ERR_CODE_MASK  (0xf << BOOTROM_ERR_CODE_OFFS)
 
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375)
+/* SAR values for Armada 375 */
+#define CONFIG_SAR_REG         (MVEBU_REGISTER(0xe8200))
+#define CONFIG_SAR2_REG                (MVEBU_REGISTER(0xe8204))
+
+#define SAR_CPU_FREQ_OFFS      17
+#define SAR_CPU_FREQ_MASK      (0x1f << SAR_CPU_FREQ_OFFS)
+
+#define BOOT_DEV_SEL_OFFS      3
+#define BOOT_DEV_SEL_MASK      (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART         0x30
+#define BOOT_FROM_SPI          0x38
+#elif defined(CONFIG_ARMADA_38X)
 /* SAR values for Armada 38x */
 #define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18600))
 
@@ -118,10 +162,30 @@
 #define BOOT_DEV_SEL_OFFS      4
 #define BOOT_DEV_SEL_MASK      (0x3f << BOOT_DEV_SEL_OFFS)
 
+#define BOOT_FROM_NAND         0x0A
+#define BOOT_FROM_SATA         0x22
 #define BOOT_FROM_UART         0x28
+#define BOOT_FROM_SATA_ALT     0x2A
+#define BOOT_FROM_UART_ALT     0x3f
 #define BOOT_FROM_SPI          0x32
 #define BOOT_FROM_MMC          0x30
 #define BOOT_FROM_MMC_ALT      0x31
+#elif defined(CONFIG_ARMADA_MSYS)
+/* SAR values for MSYS */
+#define CONFIG_SAR_REG         (MBUS_DFX_BASE  + 0xf8200)
+#define CONFIG_SAR2_REG                (MBUS_DFX_BASE  + 0xf8204)
+
+#define SAR_CPU_FREQ_OFFS      18
+#define SAR_CPU_FREQ_MASK      (0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS   11
+#define SAR_BOOT_DEVICE_MASK   (0x7 << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS      11
+#define BOOT_DEV_SEL_MASK      (0x7 << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_NAND         0x1
+#define BOOT_FROM_UART         0x2
+#define BOOT_FROM_SPI          0x3
 #else
 /* SAR values for Armada XP */
 #define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18230))