Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / mach-mvebu / include / mach / soc.h

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 01577f469b0e6bbc44a486ce59fa4639e612a816..3f3b15aa8ab6a00bb83da88d50b73ae3d57a0605 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -10,6 +10,10 @@
 #ifndef _MVEBU_SOC_H
 #define _MVEBU_SOC_H
 
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
 #define SOC_MV78230_ID         0x7823
 #define SOC_MV78260_ID         0x7826
 #define SOC_MV78460_ID         0x7846
@@ -76,7 +80,11 @@
 #define MVEBU_NAND_BASE                (MVEBU_REGISTER(0xd0000))
 #define MVEBU_SDIO_BASE                (MVEBU_REGISTER(0xd8000))
 #define MVEBU_LCD_BASE         (MVEBU_REGISTER(0xe0000))
+#ifdef CONFIG_ARMADA_MSYS
+#define MVEBU_DFX_BASE         (MBUS_DFX_BASE)
+#else
 #define MVEBU_DFX_BASE         (MVEBU_REGISTER(0xe4000))
+#endif
 
 #define SOC_COHERENCY_FABRIC_CTRL_REG  (MVEBU_REGISTER(0x20200))
 #define MBUS_ERR_PROP_EN       (1 << 8)
@@ -96,9 +104,20 @@
 #define SPI_PUP_EN             BIT(5)
 
 #define MVEBU_CORE_DIV_CLK_CTRL(i)     (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#ifdef CONFIG_ARMADA_MSYS
+#define MVEBU_DFX_DIV_CLK_CTRL(i)      (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
+#define NAND_ECC_DIVCKL_RATIO_OFFS     6
+#define NAND_ECC_DIVCKL_RATIO_MASK     (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
 #define MVEBU_DFX_DIV_CLK_CTRL(i)      (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
+#endif
+#ifdef CONFIG_ARMADA_MSYS
+#define NAND_ECC_DIVCKL_RATIO_OFFS     6
+#define NAND_ECC_DIVCKL_RATIO_MASK     (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
 #define NAND_ECC_DIVCKL_RATIO_OFFS     8
 #define NAND_ECC_DIVCKL_RATIO_MASK     (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
+#endif
 
 #define SDRAM_MAX_CS           4
 #define SDRAM_ADDR_MASK                0xFF000000
@@ -144,11 +163,29 @@
 #define BOOT_DEV_SEL_MASK      (0x3f << BOOT_DEV_SEL_OFFS)
 
 #define BOOT_FROM_NAND         0x0A
+#define BOOT_FROM_SATA         0x22
 #define BOOT_FROM_UART         0x28
+#define BOOT_FROM_SATA_ALT     0x2A
 #define BOOT_FROM_UART_ALT     0x3f
 #define BOOT_FROM_SPI          0x32
 #define BOOT_FROM_MMC          0x30
 #define BOOT_FROM_MMC_ALT      0x31
+#elif defined(CONFIG_ARMADA_MSYS)
+/* SAR values for MSYS */
+#define CONFIG_SAR_REG         (MBUS_DFX_BASE  + 0xf8200)
+#define CONFIG_SAR2_REG                (MBUS_DFX_BASE  + 0xf8204)
+
+#define SAR_CPU_FREQ_OFFS      18
+#define SAR_CPU_FREQ_MASK      (0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS   11
+#define SAR_BOOT_DEVICE_MASK   (0x7 << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS      11
+#define BOOT_DEV_SEL_MASK      (0x7 << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_NAND         0x1
+#define BOOT_FROM_UART         0x2
+#define BOOT_FROM_SPI          0x3
 #else
 /* SAR values for Armada XP */
 #define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18230))