Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

[oweals/u-boot.git] / arch / arm / mach-k3 / common.c

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 0cd34ac3c7e8a77e049db0996bac52f5363babe0..9695b2236ecd0a6d34b5292e039ac1746e40779c 100644 (file)
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -410,3 +410,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
                }
        }
 }
+
+void spl_enable_dcache(void)
+{
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+       phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+
+       dram_init_banksize();
+
+       /* reserve TLB table */
+       gd->arch.tlb_size = PGTABLE_SIZE;
+
+       ram_top += get_effective_memsize();
+       /* keep ram_top in the 32-bit address space */
+       if (ram_top >= 0x100000000)
+               ram_top = (phys_addr_t) 0x100000000;
+
+       gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+       debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+             gd->arch.tlb_addr + gd->arch.tlb_size);
+
+       dcache_enable();
+#endif
+}
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+void spl_board_prepare_for_boot(void)
+{
+       dcache_disable();
+}
+
+void spl_board_prepare_for_boot_linux(void)
+{
+       dcache_disable();
+}
+#endif