*/
#include <common.h>
+#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-rdc.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
+#include <env.h>
#include <imx_thermal.h>
#include <fsl_sec.h>
#include <asm/setup.h>
+#include <linux/delay.h>
+
+#define IOMUXC_GPR1 0x4
+#define BM_IOMUXC_GPR1_IRQ 0x1000
+
+#define GPC_LPCR_A7_BSC 0x0
+#define GPC_LPCR_M4 0x8
+#define GPC_SLPCR 0x14
+#define GPC_PGC_ACK_SEL_A7 0x24
+#define GPC_IMR1_CORE0 0x30
+#define GPC_IMR1_CORE1 0x40
+#define GPC_IMR1_M4 0x50
+#define GPC_PGC_CPU_MAPPING 0xec
+#define GPC_PGC_C0_PUPSCR 0x804
+#define GPC_PGC_SCU_TIMING 0x890
+#define GPC_PGC_C1_PUPSCR 0x844
+
+#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
+#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
+#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
+#define BM_SLPCR_EN_DSM 0x80000000
+#define BM_SLPCR_RBC_EN 0x40000000
+#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
+#define BM_SLPCR_VSTBY 0x4
+#define BM_SLPCR_SBYOS 0x2
+#define BM_SLPCR_BYPASS_PMIC_READY 0x1
+#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
+
+#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
+#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
+
+#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx7_thermal_plat = {
}
#endif
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_IMX_HAB)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
.bank = 1,
.word = 3,
}
#endif
-/* enable all periherial can be accessed in nosec mode */
-static void init_csu(void)
-{
- int i = 0;
- for (i = 0; i < CSU_NUM_REGS; i++)
- writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
-}
-
static void imx_enet_mdio_fixup(void)
{
struct iomuxc_gpr_base_regs *gpr_regs =
}
}
+static void init_cpu_basic(void)
+{
+ imx_enet_mdio_fixup();
+
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+}
+
+#ifdef CONFIG_IMX_BOOTAUX
+/*
+ * Table of mappings of physical mem regions in both
+ * Cortex-A7 and Cortex-M4 address spaces.
+ *
+ * For additional details check sections 2.1.2 and 2.1.3 in
+ * i.MX7Dual Applications Processor Reference Manual
+ *
+ */
+const struct rproc_att hostmap[] = {
+ /* aux core , host core, size */
+ { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
+ { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
+ { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
+ { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
+ { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
+ { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
+ { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
+ { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
+ { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
+ { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
+ { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
+ { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
+ { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */
+ { /* sentinel */ }
+};
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/* enable all periherial can be accessed in nosec mode */
+static void init_csu(void)
+{
+ int i = 0;
+
+ for (i = 0; i < CSU_NUM_REGS; i++)
+ writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
+}
+
+static void imx_gpcv2_init(void)
+{
+ u32 val, i;
+
+ /*
+ * Force IOMUXC irq pending, so that the interrupt to GPC can be
+ * used to deassert dsm_request signal when the signal gets
+ * asserted unexpectedly.
+ */
+ val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
+ val |= BM_IOMUXC_GPR1_IRQ;
+ writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
+
+ /* Initially mask all interrupts */
+ for (i = 0; i < 4; i++) {
+ writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
+ writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
+ writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
+ }
+
+ /* set SCU timing */
+ writel((0x59 << 10) | 0x5B | (0x2 << 20),
+ GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
+
+ /* only external IRQs to wake up LPM and core 0/1 */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
+ val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
+ writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
+
+ /* set C0 power up timming per design requirement */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
+ val &= ~BM_GPC_PGC_CORE_PUPSCR;
+ val |= (0x1A << 7);
+ writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
+
+ /* set C1 power up timming per design requirement */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
+ val &= ~BM_GPC_PGC_CORE_PUPSCR;
+ val |= (0x1A << 7);
+ writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
+
+ /* dummy ack for time slot by default */
+ writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
+ BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
+ GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
+
+ /* mask M4 DSM trigger */
+ writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
+ BM_LPCR_M4_MASK_DSM_TRIGGER,
+ GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
+
+ /* set mega/fast mix in A7 domain */
+ writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
+
+ /* DSM related settings */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
+ val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
+ BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
+ BM_SLPCR_REG_BYPASS_COUNT);
+ val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
+ writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
+
+ /*
+ * disabling RBC need to delay at least 2 cycles of CKIL(32K)
+ * due to hardware design requirement, which is
+ * ~61us, here we use 65us for safe
+ */
+ udelay(65);
+}
+
int arch_cpu_init(void)
{
init_aips();
/* Disable PDE bit of WMCR register */
imx_wdog_disable_powerdown();
- imx_enet_mdio_fixup();
-
-#ifdef CONFIG_APBH_DMA
- /* Start APBH DMA */
- mxs_dma_init();
-#endif
+ init_cpu_basic();
#if CONFIG_IS_ENABLED(IMX_RDC)
isolate_resource();
init_snvs();
+ imx_gpcv2_init();
+
return 0;
}
+#else
+int arch_cpu_init(void)
+{
+ init_cpu_basic();
+
+ return 0;
+}
+#endif
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
void reset_misc(void)
{
-#ifdef CONFIG_VIDEO_MXS
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
lcdif_power_down();
#endif
+#endif
}
projects / oweals / u-boot.git / blobdiff