common: Drop linux/delay.h from common header

[oweals/u-boot.git] / arch / arm / mach-imx / mx6 / soc.c

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 9b3d8f69b26c6157d1867663386bbaf9fcf5b9a7..19ca3826495de4d57424e5075bce624b8b1225b0 100644 (file)
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -1,13 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2007
  * Sascha Hauer, Pengutronix
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <init.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
@@ -24,12 +25,6 @@
 #include <imx_thermal.h>
 #include <mmc.h>
 
-enum ldo_reg {
-       LDO_ARM,
-       LDO_SOC,
-       LDO_PU,
-};
-
 struct scu_regs {
        u32     ctrl;
        u32     config;
@@ -51,7 +46,7 @@ U_BOOT_DEVICE(imx6_thermal) = {
 };
 #endif
 
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_IMX_HAB)
 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
        .bank = 0,
        .word = 6,
@@ -86,6 +81,10 @@ u32 get_cpu_rev(void)
                                type = MXC_CPU_MX6D;
                }
 
+               if (type == MXC_CPU_MX6ULL) {
+                       if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
+                               type = MXC_CPU_MX6ULZ;
+               }
        }
        major = ((reg >> 8) & 0xff);
        if ((major >= 1) &&
@@ -96,6 +95,11 @@ u32 get_cpu_rev(void)
                        type = MXC_CPU_MX6DP;
        }
        reg &= 0xff;            /* mx6 silicon revision */
+
+       /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
+       if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
+               reg = 0x3;
+
        return (type << 12) | (reg + (0x10 * (major + 1)));
 }
 
@@ -246,7 +250,7 @@ static void clear_ldo_ramp(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
+int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
        u32 val, step, old, reg = readl(&anatop->reg_core);
@@ -366,6 +370,37 @@ static void init_bandgap(void)
        }
 }
 
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+static void noc_setup(void)
+{
+       enable_ipu_clock();
+
+       writel(0x80000201, 0xbb0608);
+       /* Bypass IPU1 QoS generator */
+       writel(0x00000002, 0x00bb048c);
+       /* Bypass IPU2 QoS generator */
+       writel(0x00000002, 0x00bb050c);
+       /* Bandwidth THR for of PRE0 */
+       writel(0x00000200, 0x00bb0690);
+       /* Bandwidth THR for of PRE1 */
+       writel(0x00000200, 0x00bb0710);
+       /* Bandwidth THR for of PRE2 */
+       writel(0x00000200, 0x00bb0790);
+       /* Bandwidth THR for of PRE3 */
+       writel(0x00000200, 0x00bb0810);
+       /* Saturation THR for of PRE0 */
+       writel(0x00000010, 0x00bb0694);
+       /* Saturation THR for of PRE1 */
+       writel(0x00000010, 0x00bb0714);
+       /* Saturation THR for of PRE2 */
+       writel(0x00000010, 0x00bb0794);
+       /* Saturation THR for of PRE */
+       writel(0x00000010, 0x00bb0814);
+
+       disable_ipu_clock();
+}
+#endif
+
 int arch_cpu_init(void)
 {
        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -443,6 +478,10 @@ int arch_cpu_init(void)
 
        init_src();
 
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+       if (is_mx6dqp())
+               noc_setup();
+#endif
        return 0;
 }
 
@@ -549,9 +588,11 @@ const struct boot_mode soc_boot_modes[] = {
 
 void reset_misc(void)
 {
-#ifdef CONFIG_VIDEO_MXS
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
        lcdif_power_down();
 #endif
+#endif
 }
 
 void s_init(void)
@@ -650,10 +691,23 @@ void imx_setup_hdmi(void)
 }
 #endif
 
+
+/*
+ * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
+ * MX6Q and MX6QP processors
+ */
 void gpr_init(void)
 {
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
+       /*
+        * If this function is used in a common MX6 spl implementation
+        * we have to ensure that it is only called for suitable cpu types,
+        * otherwise it breaks hardware parts like enet1, can1, can2, etc.
+        */
+       if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
+               return;
+
        /* enable AXI cache for VDOA/VPU/IPU */
        writel(0xF00000CF, &iomux->gpr[4]);
        if (is_mx6dqp()) {