common: Drop linux/delay.h from common header

[oweals/u-boot.git] / arch / arm / mach-imx / mx6 / soc.c

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 926718b49c0e452e1e798b565a01a4e40fb1bbca..19ca3826495de4d57424e5075bce624b8b1225b0 100644 (file)
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <init.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
@@ -24,12 +25,6 @@
 #include <imx_thermal.h>
 #include <mmc.h>
 
-enum ldo_reg {
-       LDO_ARM,
-       LDO_SOC,
-       LDO_PU,
-};
-
 struct scu_regs {
        u32     ctrl;
        u32     config;
@@ -255,7 +250,7 @@ static void clear_ldo_ramp(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
+int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
        u32 val, step, old, reg = readl(&anatop->reg_core);
@@ -375,6 +370,37 @@ static void init_bandgap(void)
        }
 }
 
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+static void noc_setup(void)
+{
+       enable_ipu_clock();
+
+       writel(0x80000201, 0xbb0608);
+       /* Bypass IPU1 QoS generator */
+       writel(0x00000002, 0x00bb048c);
+       /* Bypass IPU2 QoS generator */
+       writel(0x00000002, 0x00bb050c);
+       /* Bandwidth THR for of PRE0 */
+       writel(0x00000200, 0x00bb0690);
+       /* Bandwidth THR for of PRE1 */
+       writel(0x00000200, 0x00bb0710);
+       /* Bandwidth THR for of PRE2 */
+       writel(0x00000200, 0x00bb0790);
+       /* Bandwidth THR for of PRE3 */
+       writel(0x00000200, 0x00bb0810);
+       /* Saturation THR for of PRE0 */
+       writel(0x00000010, 0x00bb0694);
+       /* Saturation THR for of PRE1 */
+       writel(0x00000010, 0x00bb0714);
+       /* Saturation THR for of PRE2 */
+       writel(0x00000010, 0x00bb0794);
+       /* Saturation THR for of PRE */
+       writel(0x00000010, 0x00bb0814);
+
+       disable_ipu_clock();
+}
+#endif
+
 int arch_cpu_init(void)
 {
        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -452,6 +478,10 @@ int arch_cpu_init(void)
 
        init_src();
 
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+       if (is_mx6dqp())
+               noc_setup();
+#endif
        return 0;
 }