ARM: at91: mpddrc: add lpddr2 initialization procedure

[oweals/u-boot.git] / arch / arm / mach-at91 / include / mach / atmel_mpddrc.h

diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index 45a76a60fa2c09aaee81a285904ebbbe4add1507..40ec87e2ff94651a1d69589df8fb84b2afc98b68 100644 (file)
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -18,6 +18,9 @@ struct atmel_mpddrc_config {
        u32 tpr1;
        u32 tpr2;
        u32 md;
+       u32 lpddr23_lpr;
+       u32 cal_mr4;
+       u32 tim_cal;
 };
 
 /*
@@ -61,6 +64,10 @@ int ddr2_init(const unsigned int base,
              const unsigned int ram_address,
              const struct atmel_mpddrc_config *mpddr_value);
 
+int lpddr2_init(const unsigned int base,
+               const unsigned int ram_address,
+               const struct atmel_mpddrc_config *mpddr_value);
+
 int ddr3_init(const unsigned int base,
              const unsigned int ram_address,
              const struct atmel_mpddrc_config *mpddr_value);
@@ -74,6 +81,11 @@ int ddr3_init(const unsigned int base,
 #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD       0x5
 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD          0x6
 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD                0x7
+#define ATMEL_MPDDRC_MR_MRS(v)                 (((v) & 0xFF) << 0x8)
+
+/* Bit field in refresh timer register */
+#define ATMEL_MPDDRC_RTR_ADJ_REF               (0x1 << 16)
+#define ATMEL_MPDDRC_RTR_MR4VALUE(v)           (((v) & 0x7) << 20)
 
 /* Bit field in configuration register */
 #define ATMEL_MPDDRC_CR_NC_MASK                        0x3
@@ -157,6 +169,7 @@ int ddr3_init(const unsigned int base,
 #define ATMEL_MPDDRC_MD_DDR3_SDRAM     0x4
 #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM   0x5
 #define ATMEL_MPDDRC_MD_DDR2_SDRAM     0x6
+#define ATMEL_MPDDRC_MD_LPDDR2_SDRAM   0x7
 #define ATMEL_MPDDRC_MD_DBW_MASK       (0x1 << 4)
 #define ATMEL_MPDDRC_MD_DBW_32_BITS    (0x0 << 4)
 #define ATMEL_MPDDRC_MD_DBW_16_BITS    (0x1 << 4)
@@ -206,4 +219,14 @@ int ddr3_init(const unsigned int base,
 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE      0x2
 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE    0x3
 
+/* Bit field in LPDDR2 - LPDDR3 Low Power Register */
+#define ATMEL_MPDDRC_LPDDR23_LPR_DS(x)                 (((x) & 0xf) << 24)
+
+/* Bit field in CAL_MR4 Calibration and MR4 Register */
+#define ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(x)              (((x) & 0xffff) << 0)
+#define ATMEL_MPDDRC_CAL_MR4_MR4R(x)                   (((x) & 0xffff) << 16)
+
+/* Bit field in TIM_CAL Timing Calibration Register */
+#define ATMEL_MPDDRC_CALR_ZQCS(x)                      (((x) & 0xff) << 0)
+
 #endif