mach-imx: bootaux: elf firmware support

[oweals/u-boot.git] / arch / arm / include / asm / mach-imx / sys_proto.h

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index c53e5400a1d3c0afc26442ee3d45ac84093d6fd0..fff48008087a0abc007d27dc0b3800d71afe0f7f 100644 (file)
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2009
  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _SYS_PROTO_H_
@@ -27,6 +26,8 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
+#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
+#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
@@ -37,10 +38,25 @@
 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
 
 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
 
+#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
+#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
+       is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
+       is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
+#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
+#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
+#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
+#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN))
+
+#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
+
 #ifdef CONFIG_MX6
 #define IMX6_SRC_GPR10_BMODE           BIT(28)
 
@@ -63,8 +79,8 @@ enum imx6_bmode_serial_rom {
 };
 
 enum imx6_bmode_emi {
-       IMX6_BMODE_ONENAND,
        IMX6_BMODE_NOR,
+       IMX6_BMODE_ONENAND,
 };
 
 enum imx6_bmode {
@@ -85,16 +101,51 @@ enum imx6_bmode {
        IMX6_BMODE_NAND_MAX = 0xf,
 };
 
-static inline u8 imx6_is_bmode_from_gpr9(void)
-{
-       return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
-}
-
 u32 imx6_src_get_boot_mode(void);
 void gpr_init(void);
 
 #endif /* CONFIG_MX6 */
 
+/* address translation table */
+struct rproc_att {
+       u32 da; /* device address (From Cortex M4 view) */
+       u32 sa; /* system bus address */
+       u32 size; /* size of reg range */
+};
+
+#ifdef CONFIG_IMX8M
+struct rom_api {
+       u16 ver;
+       u16 tag;
+       u32 reserved1;
+       u32 (*download_image)(u8 *dest, u32 offset, u32 size,  u32 xor);
+       u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
+};
+
+enum boot_dev_type_e {
+       BT_DEV_TYPE_SD = 1,
+       BT_DEV_TYPE_MMC = 2,
+       BT_DEV_TYPE_NAND = 3,
+       BT_DEV_TYPE_FLEXSPINOR = 4,
+
+       BT_DEV_TYPE_USB = 0xE,
+       BT_DEV_TYPE_MEM_DEV = 0xF,
+
+       BT_DEV_TYPE_INVALID = 0xFF
+};
+
+#define QUERY_ROM_VER          1
+#define QUERY_BT_DEV           2
+#define QUERY_PAGE_SZ          3
+#define QUERY_IVT_OFF          4
+#define QUERY_BT_STAGE         5
+#define QUERY_IMG_OFF          6
+
+#define ROM_API_OKAY           0xF0
+
+extern struct rom_api *g_rom_api;
+#endif
+
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
 u32 get_cpu_speed_grade_hz(void);
@@ -106,8 +157,11 @@ void set_chipselect_size(int const);
 
 void init_aips(void);
 void init_src(void);
+void init_snvs(void);
 void imx_wdog_disable_powerdown(void);
 
+int arch_auxiliary_core_check_up(u32 core_id);
+
 int board_mmc_get_env_dev(int devno);
 
 int nxp_board_rev(void);
@@ -128,5 +182,9 @@ int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 
 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
-                          unsigned long reg1, unsigned long reg2);
+                          unsigned long reg1, unsigned long reg2,
+                          unsigned long reg3);
+unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
+                               unsigned long *reg1, unsigned long reg2,
+                               unsigned long reg3);
 #endif