#endif /* CONFIG_MX6 */
+/* address translation table */
+struct rproc_att {
+ u32 da; /* device address (From Cortex M4 view) */
+ u32 sa; /* system bus address */
+ u32 size; /* size of reg range */
+};
+
+#ifdef CONFIG_IMX8M
+struct rom_api {
+ u16 ver;
+ u16 tag;
+ u32 reserved1;
+ u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
+ u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
+};
+
+enum boot_dev_type_e {
+ BT_DEV_TYPE_SD = 1,
+ BT_DEV_TYPE_MMC = 2,
+ BT_DEV_TYPE_NAND = 3,
+ BT_DEV_TYPE_FLEXSPINOR = 4,
+
+ BT_DEV_TYPE_USB = 0xE,
+ BT_DEV_TYPE_MEM_DEV = 0xF,
+
+ BT_DEV_TYPE_INVALID = 0xFF
+};
+
+#define QUERY_ROM_VER 1
+#define QUERY_BT_DEV 2
+#define QUERY_PAGE_SZ 3
+#define QUERY_IVT_OFF 4
+#define QUERY_BT_STAGE 5
+#define QUERY_IMG_OFF 6
+
+#define ROM_API_OKAY 0xF0
+
+extern struct rom_api *g_rom_api;
+#endif
+
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_speed_grade_hz(void);
void init_snvs(void);
void imx_wdog_disable_powerdown(void);
+int arch_auxiliary_core_check_up(u32 core_id);
+
int board_mmc_get_env_dev(int devno);
int nxp_board_rev(void);