Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / include / asm / mach-imx / regs-bch.h

diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h
index 39ac5f4d450021d7e4e7002f29d5c297f85d9b78..5a149002e2a79a565a089782be9c171955728626 100644 (file)
--- a/arch/arm/include/asm/mach-imx/regs-bch.h
+++ b/arch/arm/include/asm/mach-imx/regs-bch.h
@@ -6,7 +6,9 @@
  * on behalf of DENX Software Engineering GmbH
  *
  * Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2020 NXP
+ *
  */
 
 #ifndef __MX28_REGS_BCH_H__
@@ -40,6 +42,7 @@ struct mxs_bch_regs {
        mxs_reg_32(hw_bch_dbgahbmread)
        mxs_reg_32(hw_bch_blockname)
        mxs_reg_32(hw_bch_version)
+       mxs_reg_32(hw_bch_debug1)
 };
 #endif
 
@@ -75,6 +78,9 @@ struct mxs_bch_regs {
 
 #define        BCH_MODE_ERASE_THRESHOLD_MASK                   0xff
 #define        BCH_MODE_ERASE_THRESHOLD_OFFSET                 0
+#define BCH_MODE_ERASE_THRESHOLD(v)                    \
+       (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) &     \
+        BCH_MODE_ERASE_THRESHOLD_MASK)
 
 #define        BCH_ENCODEPTR_ADDR_MASK                         0xffffffff
 #define        BCH_ENCODEPTR_ADDR_OFFSET                       0
@@ -122,7 +128,7 @@ struct mxs_bch_regs {
 #define        BCH_FLASHLAYOUT0_NBLOCKS_OFFSET                 24
 #define        BCH_FLASHLAYOUT0_META_SIZE_MASK                 (0xff << 16)
 #define        BCH_FLASHLAYOUT0_META_SIZE_OFFSET               16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
 #define        BCH_FLASHLAYOUT0_ECC0_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT0_ECC0_OFFSET                    11
 #else
@@ -146,14 +152,14 @@ struct mxs_bch_regs {
 #define        BCH_FLASHLAYOUT0_ECC0_ECC28                     (0xe << 12)
 #define        BCH_FLASHLAYOUT0_ECC0_ECC30                     (0xf << 12)
 #define        BCH_FLASHLAYOUT0_ECC0_ECC32                     (0x10 << 12)
-#define        BCH_FLASHLAYOUT0_GF13_0_GF14_1                  (1 << 10)
+#define        BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK             BIT(10)
 #define        BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET           10
-#define        BCH_FLASHLAYOUT0_DATA0_SIZE_MASK                0xfff
+#define        BCH_FLASHLAYOUT0_DATA0_SIZE_MASK                0x3ff
 #define        BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET              0
 
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_MASK                 (0xffff << 16)
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET               16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
 #define        BCH_FLASHLAYOUT1_ECCN_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT1_ECCN_OFFSET                    11
 #else
@@ -177,9 +183,9 @@ struct mxs_bch_regs {
 #define        BCH_FLASHLAYOUT1_ECCN_ECC28                     (0xe << 12)
 #define        BCH_FLASHLAYOUT1_ECCN_ECC30                     (0xf << 12)
 #define        BCH_FLASHLAYOUT1_ECCN_ECC32                     (0x10 << 12)
-#define        BCH_FLASHLAYOUT1_GF13_0_GF14_1                  (1 << 10)
+#define        BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK             BIT(10)
 #define        BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET           10
-#define        BCH_FLASHLAYOUT1_DATAN_SIZE_MASK                0xfff
+#define        BCH_FLASHLAYOUT1_DATAN_SIZE_MASK                0x3ff
 #define        BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET              0
 
 #define        BCH_DEBUG0_RSVD1_MASK                           (0x1f << 27)