Merge branch 'master' of git://git.denx.de/u-boot-video

[oweals/u-boot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ed251ec8ec19f119180e56a7be186bcc6110fbab..d9d521a51505728eff9e04674516aba66ce3b222 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -519,6 +519,7 @@
 
 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES     0x0000C1A7
 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES      0x000001A7
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
 
 /* DMM */
 #define DMM_BASE                       0x4E000040
@@ -580,7 +581,6 @@
        (0xFF << EMIF_SYS_ADDR_SHIFT))
 
 #define EMIF_EXT_PHY_CTRL_TIMING_REG   0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG    0x13
 
 /* Reg mapping structure */
 struct emif_reg_struct {
@@ -640,7 +640,9 @@ struct emif_reg_struct {
        u32 emif_ddr_phy_ctrl_2;
        u32 padding7[12];
        u32 emif_rd_wr_exec_thresh;
-       u32 padding8[55];
+       u32 padding8[7];
+       u32 emif_ddr_phy_status[21];
+       u32 padding9[27];
        u32 emif_ddr_ext_phy_ctrl_1;
        u32 emif_ddr_ext_phy_ctrl_1_shdw;
        u32 emif_ddr_ext_phy_ctrl_2;
@@ -689,6 +691,9 @@ struct emif_reg_struct {
        u32 emif_ddr_ext_phy_ctrl_23_shdw;
        u32 emif_ddr_ext_phy_ctrl_24;
        u32 emif_ddr_ext_phy_ctrl_24_shdw;
+       u32 padding[22];
+       u32 emif_ddr_fifo_misaligned_clear_1;
+       u32 emif_ddr_fifo_misaligned_clear_2;
 };
 
 struct dmm_lisa_map_regs {
@@ -696,11 +701,9 @@ struct dmm_lisa_map_regs {
        u32 dmm_lisa_map_1;
        u32 dmm_lisa_map_2;
        u32 dmm_lisa_map_3;
+       u8 is_ma_present;
 };
 
-extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
 #define CS0    0
 #define CS1    1
 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -856,13 +859,10 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 #define DPD_ENABLE     1
 
 /* Maximum delay before Low Power Modes */
-#ifndef CONFIG_OMAP54XX
-#define REG_CS_TIM             0xF
-#else
 #define REG_CS_TIM             0x0
-#endif
-#define REG_SR_TIM             0xF
-#define REG_PD_TIM             0xF
+#define REG_SR_TIM             0x0
+#define REG_PD_TIM             0x0
+
 
 /* EMIF_PWR_MGMT_CTRL register */
 #define EMIF_PWR_MGMT_CTRL (\
@@ -1027,6 +1027,11 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 #define MR8_IO_WIDTH_SHIFT     0x6
 #define MR8_IO_WIDTH_MASK      (0x3 << 0x6)
 
+/* SDRAM TYPE */
+#define EMIF_SDRAM_TYPE_DDR2   0x2
+#define EMIF_SDRAM_TYPE_DDR3   0x3
+#define EMIF_SDRAM_TYPE_LPDDR2 0x4
+
 struct lpddr2_addressing {
        u8      num_banks;
        u8      t_REFI_us_x10;
@@ -1109,6 +1114,7 @@ struct emif_regs {
        u32 freq;
        u32 sdram_config_init;
        u32 sdram_config;
+       u32 sdram_config2;
        u32 ref_ctrl;
        u32 sdram_tim1;
        u32 sdram_tim2;
@@ -1129,6 +1135,19 @@ struct emif_regs {
        u32 emif_rd_wr_exec_thresh;
 };
 
+struct lpddr2_mr_regs {
+       s8 mr1;
+       s8 mr2;
+       s8 mr3;
+       s8 mr10;
+       s8 mr16;
+};
+
+struct read_write_regs {
+       u32 read_reg;
+       u32 write_reg;
+};
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c) ({ if (!(c)) for (;;); })
@@ -1148,12 +1167,14 @@ void emif_get_device_timings(u32 emif_nr,
 #endif
 
 void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 extern u32 *const T_num;
 extern u32 *const T_den;
-extern u32 *const emif_sizes;
 #endif
 
 void config_data_eye_leveling_samples(u32 emif_base);
+u32 emif_sdram_type(void);
+const struct read_write_regs *get_bug_regs(u32 *iterations);
 #endif