Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / include / asm / arch-vf610 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 975832343316947ec13aca511cc39a58e7e250d0..97211f4b12af4f082ebc667eb11a2812ef6635a5 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2013-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __ASM_ARCH_IMX_REGS_H__
@@ -69,6 +68,7 @@
 #define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
 #define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
 #define SCSC_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00058000)
 #define ASRC_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR                (AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00062000)
@@ -98,6 +98,7 @@
 #define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
 #define ENET_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00058000)
 #define NFC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00060000)
 
 #define QSPI0_AMBA_BASE                0x20000000
@@ -199,21 +200,34 @@
 #define DDRMC_CR78_Q_FULLNESS(v)                       (((v) & 0x7) << 24)
 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)                   ((v) & 0xf)
 #define DDRMC_CR79_CTLUPD_AREF(v)                      (((v) & 0x1) << 24)
-#define DDRMC_CR82_INT_MASK                            0x10000000
+#define DDRMC_CR80_MC_INIT_COMPLETE                    (1 << 8)
+#define DDRMC_CR82_INT_MASK                            (1 << 28)
 #define DDRMC_CR87_ODT_WR_MAPCS0(v)                    ((v) << 24)
 #define DDRMC_CR87_ODT_RD_MAPCS0(v)                    ((v) << 16)
 #define DDRMC_CR88_TODTL_CMD(v)                                (((v) & 0x1f) << 16)
 #define DDRMC_CR89_AODT_RWSMCS(v)                      ((v) & 0xf)
 #define DDRMC_CR91_R2W_SMCSDL(v)                       (((v) & 0x7) << 16)
+#define DDRMC_CR93_SW_LVL_MODE_OFF                     (8)
+#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF)
+#define DDRMC_CR93_SWLVL_LOAD                          BIT(16)
+#define DDRMC_CR93_SWLVL_START                         BIT(24)
+#define DDRMC_CR94_SWLVL_EXIT                          BIT(0)
+#define DDRMC_CR94_SWLVL_OP_DONE                       BIT(8)
+#define DDRMC_CR94_SWLVL_RESP_0_OFF                    (24)
+#define DDRMC_CR95_SWLVL_RESP_1_OFF                    (0)
 #define DDRMC_CR96_WLMRD(v)                            (((v) & 0x3f) << 8)
 #define DDRMC_CR96_WLDQSEN(v)                          ((v) & 0x3f)
 #define DDRMC_CR97_WRLVL_EN                            (1 << 24)
 #define DDRMC_CR98_WRLVL_DL_0(v)                       ((v) & 0xffff)
 #define DDRMC_CR99_WRLVL_DL_1(v)                       ((v) & 0xffff)
+#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF                 (24)
+#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF)
 #define DDRMC_CR102_RDLVL_GT_REGEN                     (1 << 16)
 #define DDRMC_CR102_RDLVL_REG_EN                       (1 << 8)
-#define DDRMC_CR105_RDLVL_DL_0(v)                      (((v) & 0xff) << 8)
+#define DDRMC_CR105_RDLVL_DL_0_OFF                     (8)
+#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF)
 #define DDRMC_CR106_RDLVL_GTDL_0(v)                    ((v) & 0xff)
+#define DDRMC_CR110_RDLVL_DL_1_OFF                     (0)
 #define DDRMC_CR110_RDLVL_DL_1(v)                      ((v) & 0xff)
 #define DDRMC_CR110_RDLVL_GTDL_1(v)                    (((v) & 0xff) << 16)
 #define DDRMC_CR114_RDLVL_GTDL_2(v)                    (((v) & 0xffff) << 8)
@@ -238,7 +252,7 @@
 #define DDRMC_CR132_RDLAT_ADJ(v)                       ((v) & 0x3f)
 #define DDRMC_CR137_PHYCTL_DL(v)                       (((v) & 0xf) << 16)
 #define DDRMC_CR138_PHY_WRLV_MXDL(v)                   (((v) & 0xffff) << 16)
-#define DDRMC_CR138_PHYDRAM_CK_EN(v)                   (((v) & 0x8) << 8)
+#define DDRMC_CR138_PHYDRAM_CK_EN(v)                   (((v) & 0x7) << 8)
 #define DDRMC_CR139_PHY_WRLV_RESPLAT(v)                        (((v) & 0xff) << 24)
 #define DDRMC_CR139_PHY_WRLV_LOAD(v)                   (((v) & 0xff) << 16)
 #define DDRMC_CR139_PHY_WRLV_DLL(v)                    (((v) & 0xff) << 8)
@@ -275,6 +289,8 @@
 #define SRC_SRSR_WDOG_M4                               (0x1 << 4)
 #define SRC_SRSR_WDOG_A5                               (0x1 << 3)
 #define SRC_SRSR_POR_RST                               (0x1 << 0)
+#define SRC_SBMR1_BOOTCFG1_SDMMC        BIT(6)
+#define SRC_SBMR1_BOOTCFG1_MMC          BIT(4)
 #define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
 #define SRC_SBMR2_BMOD_SHIFT            24
 #define SRC_SBMR2_BMOD_FUSES            0x0
@@ -286,6 +302,7 @@
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
+#include <linux/bitops.h>
 
 /* System Reset Controller (SRC) */
 struct src {
@@ -429,34 +446,6 @@ struct fuse_bank4_regs {
        u32 rsvd7[3];
 };
 
-/* UART */
-struct lpuart_fsl {
-       u8 ubdh;
-       u8 ubdl;
-       u8 uc1;
-       u8 uc2;
-       u8 us1;
-       u8 us2;
-       u8 uc3;
-       u8 ud;
-       u8 uma1;
-       u8 uma2;
-       u8 uc4;
-       u8 uc5;
-       u8 ued;
-       u8 umodem;
-       u8 uir;
-       u8 reserved;
-       u8 upfifo;
-       u8 ucfifo;
-       u8 usfifo;
-       u8 utwfifo;
-       u8 utcfifo;
-       u8 urwfifo;
-       u8 urcfifo;
-       u8 rsvd[28];
-};
-
 /* MSCM Interrupt Router */
 struct mscm_ir {
        u32 ircp0ir;
@@ -486,6 +475,6 @@ struct mscm {
        u32 cpxcfg3;
 };
 
-#endif /* __ASSEMBLER__*/
+#endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_ARCH_IMX_REGS_H__ */