SPDX: Convert all of our single license tags to Linux Kernel style

[oweals/u-boot.git] / arch / arm / include / asm / arch-tegra / tegra.h

diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 5fe4838d9beaefe88bc984aa8ee66ceb7c4d2602..7ae0129e2db3d65b08cae7ba7b23849779658ce3 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -1,24 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #ifndef _TEGRA_H_
@@ -50,7 +33,12 @@
 #define NV_PA_PMC_BASE         (NV_PA_APB_MISC_BASE + 0xE400)
 #define NV_PA_EMC_BASE         (NV_PA_APB_MISC_BASE + 0xF400)
 #define NV_PA_FUSE_BASE                (NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+       defined(CONFIG_TEGRA114)
 #define NV_PA_CSITE_BASE       0x70040000
+#else
+#define NV_PA_CSITE_BASE       0x70800000
+#endif
 #define TEGRA_USB_ADDR_MASK    0xFFFFC000
 
 #define NV_PA_SDRC_CS0         NV_PA_SDRAM_BASE
@@ -67,6 +55,8 @@ struct timerus {
 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
 #define NV_WB_RUN_ADDRESS      0x40020000
 
+#define NVBOOTTYPE_RECOVERY    2       /* BR entered RCM */
+#define NVBOOTINFOTABLE_BOOTTYPE 0xC   /* Boot type in BIT in IRAM */
 #define NVBOOTINFOTABLE_BCTSIZE        0x38    /* BCT size in BIT in IRAM */
 #define NVBOOTINFOTABLE_BCTPTR 0x3C    /* BCT pointer in BIT in IRAM */
 
@@ -81,8 +71,11 @@ enum {
        SKU_ID_T25E             = 0x1c,
        SKU_ID_T33              = 0x80,
        SKU_ID_T30              = 0x81, /* Cardhu value */
+       SKU_ID_TM30MQS_P_A3     = 0xb1,
        SKU_ID_T114_ENG         = 0x00, /* Dalmore value, unfused */
        SKU_ID_T114_1           = 0x01,
+       SKU_ID_T124_ENG         = 0x00, /* Venice2 value, unfused */
+       SKU_ID_T210_ENG         = 0x00, /* unfused value TBD */
 };
 
 /*
@@ -96,11 +89,18 @@ enum {
        TEGRA_SOC_T25,
        TEGRA_SOC_T30,
        TEGRA_SOC_T114,
+       TEGRA_SOC_T124,
+       TEGRA_SOC_T210,
 
        TEGRA_SOC_CNT,
        TEGRA_SOC_UNKNOWN       = -1,
 };
 
+/* Tegra system controller (SYSCON) devices */
+enum {
+       TEGRA_SYSCON_PMC,
+};
+
 #else  /* __ASSEMBLY__ */
 #define PRM_RSTCTRL            NV_PA_PMC_BASE
 #endif