Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...
[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h
index 7670b56c94e99a9b19976d84b730f4a88b8369f2..baa9fa8529cdb915696103bb4d75649f3d792529 100644 (file)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#ifndef CONFIG_NXP_LSCH3_2
 #define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x010c0000)
+#else
+#define SYS_NXP_FSPI_ADDR                      (CONFIG_SYS_IMMR + 0x010c0000)
+#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR          0x18
+#define SYS_NXP_FSPI_LUT_BASE_ADDR             0x200
+#endif
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
 #define FSL_ESDHC1_BASE_ADDR                   CONFIG_SYS_FSL_ESDHC_ADDR
 #define FSL_ESDHC2_BASE_ADDR                   (CONFIG_SYS_IMMR + 0x01150000)
 #define DCFG_PORSR1                    0x000
 #define DCFG_PORSR1_RCW_SRC            0xff800000
 #define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
+#define DCFG_RCWSR12                   0x12c
+#define DCFG_RCWSR12_SDHC_SHIFT                24
+#define DCFG_RCWSR12_SDHC_MASK         0x7
 #define DCFG_RCWSR13                   0x130
+#define DCFG_RCWSR13_SDHC_SHIFT                3
+#define DCFG_RCWSR13_SDHC_MASK         0x7
 #define DCFG_RCWSR13_DSPI              (0 << 8)
 #define DCFG_RCWSR15                   0x138
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
@@ -578,5 +589,5 @@ struct ccsr_serdes {
        u8 res5[0x19fc - 0xa00];
 };
 
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLY__ */
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */