#define DCFG_PORSR1 0x000
#define DCFG_PORSR1_RCW_SRC 0xff800000
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
+#define DCFG_RCWSR12 0x12c
+#define DCFG_RCWSR12_SDHC_SHIFT 24
+#define DCFG_RCWSR12_SDHC_MASK 0x7
#define DCFG_RCWSR13 0x130
+#define DCFG_RCWSR13_SDHC_SHIFT 3
+#define DCFG_RCWSR13_SDHC_MASK 0x7
#define DCFG_RCWSR13_DSPI (0 << 8)
#define DCFG_RCWSR15 0x138
#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
u8 res5[0x19fc - 0xa00];
};
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLY__ */
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */