Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 24c1b0e482eb48c71dcdf351d4912d8e2fdbb2d8..baa9fa8529cdb915696103bb4d75649f3d792529 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -23,8 +23,16 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#ifndef CONFIG_NXP_LSCH3_2
 #define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x010c0000)
+#else
+#define SYS_NXP_FSPI_ADDR                      (CONFIG_SYS_IMMR + 0x010c0000)
+#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR          0x18
+#define SYS_NXP_FSPI_LUT_BASE_ADDR             0x200
+#endif
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR                   CONFIG_SYS_FSL_ESDHC_ADDR
+#define FSL_ESDHC2_BASE_ADDR                   (CONFIG_SYS_IMMR + 0x01150000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x01240000)
 #endif
@@ -79,9 +87,24 @@
 #define TZASC_REGION_ATTRIBUTES_0(x)   ((TZASC1_BASE + (x * 0x10000)) + 0x110)
 #define TZASC_REGION_ID_ACCESS_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x114)
 
+/* EDMA */
+#define EDMA_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x012c0000)
+
 /* SATA */
 #define AHCI_BASE_ADDR1                                (CONFIG_SYS_IMMR + 0x02200000)
 #define AHCI_BASE_ADDR2                                (CONFIG_SYS_IMMR + 0x02210000)
+#define AHCI_BASE_ADDR3                                (CONFIG_SYS_IMMR + 0x02220000)
+#define AHCI_BASE_ADDR4                                (CONFIG_SYS_IMMR + 0x02230000)
+
+/* QDMA */
+#define QDMA_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG                                0x20a80
+
+/* DISPLAY */
+#define DISPLAY_BASE_ADDR                      (CONFIG_SYS_IMMR + 0x0e080000)
+
+/* GPU */
+#define GPU_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x0e0c0000)
 
 /* SFP */
 #define CONFIG_SYS_SFP_ADDR            (CONFIG_SYS_IMMR + 0x00e80200)
@@ -89,10 +112,18 @@
 /* SEC */
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x07000000ull
 #define CONFIG_SYS_FSL_JR0_OFFSET              0x07010000ull
+#define FSL_SEC_JR0_OFFSET                     CONFIG_SYS_FSL_JR0_OFFSET
+#define FSL_SEC_JR1_OFFSET                     0x07020000ull
+#define FSL_SEC_JR2_OFFSET                     0x07030000ull
+#define FSL_SEC_JR3_OFFSET                     0x07040000ull
 #define CONFIG_SYS_FSL_SEC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
 
 #ifdef CONFIG_TFABOOT
 #ifdef CONFIG_NXP_LSCH3_2
@@ -186,6 +217,9 @@
 #elif CONFIG_ARCH_LS1028A
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x01f0000000ULL
+/* this is used by integrated PCI on LS1028, includes ECAM and register space */
+#define CONFIG_SYS_PCIE3_PHYS_SIZE             0x0010000000ULL
 #else
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x1000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x1200000000ULL
@@ -198,7 +232,12 @@
 #define DCFG_PORSR1                    0x000
 #define DCFG_PORSR1_RCW_SRC            0xff800000
 #define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
+#define DCFG_RCWSR12                   0x12c
+#define DCFG_RCWSR12_SDHC_SHIFT                24
+#define DCFG_RCWSR12_SDHC_MASK         0x7
 #define DCFG_RCWSR13                   0x130
+#define DCFG_RCWSR13_SDHC_SHIFT                3
+#define DCFG_RCWSR13_SDHC_MASK         0x7
 #define DCFG_RCWSR13_DSPI              (0 << 8)
 #define DCFG_RCWSR15                   0x138
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
@@ -224,8 +263,16 @@
 #define DCSR_USB_PHY_RX_OVRD_IN_HI     0x200C
 #define USB_PHY_RX_EQ_VAL_1            0x0000
 #define USB_PHY_RX_EQ_VAL_2            0x0080
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
+       defined(CONFIG_ARCH_LS1028A)
 #define USB_PHY_RX_EQ_VAL_3            0x0380
 #define USB_PHY_RX_EQ_VAL_4            0x0b80
+#elif defined(CONFIG_ARCH_LX2160A)
+#define USB_PHY_RX_EQ_VAL_3            0x0080
+#define USB_PHY_RX_EQ_VAL_4            0x0880
+#endif
+#define DCSR_USB_IOCR1                 0x108004
+#define DCSR_USB_PCSTXSWINGFULL        0x71
 
 #define TP_ITYP_AV             0x00000001      /* Initiator available */
 #define TP_ITYP_TYPE(x)        (((x) & 0x6) >> 1)      /* Initiator Type */
@@ -250,6 +297,7 @@ struct sys_info {
        /* frequency of platform PLL */
        unsigned long freq_systembus;
        unsigned long freq_ddrbus;
+       unsigned long freq_cga_m2;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
        unsigned long freq_ddrbus2;
 #endif
@@ -412,15 +460,19 @@ struct ccsr_gur {
        u32     usb2_amqr;
        u8      res_528[0x530-0x528];   /* add more registers when needed */
        u32     sdmm1_amqr;
-       u8      res_534[0x550-0x534];   /* add more registers when needed */
+       u32     sdmm2_amqr;
+       u8      res_538[0x550 - 0x538]; /* add more registers when needed */
        u32     sata1_amqr;
        u32     sata2_amqr;
-       u8      res_558[0x570-0x558];   /* add more registers when needed */
+       u32     sata3_amqr;
+       u32     sata4_amqr;
+       u8      res_560[0x570 - 0x560]; /* add more registers when needed */
        u32     misc1_amqr;
        u8      res_574[0x590-0x574];   /* add more registers when needed */
        u32     spare1_amqr;
        u32     spare2_amqr;
-       u8      res_598[0x620-0x598];   /* add more registers when needed */
+       u32     spare3_amqr;
+       u8      res_59c[0x620 - 0x59c]; /* add more registers when needed */
        u32     gencr[7];       /* General Control Registers */
        u8      res_63c[0x640-0x63c];   /* add more registers when needed */
        u32     cgensr1;        /* Core General Status Register */
@@ -537,5 +589,5 @@ struct ccsr_serdes {
        u8 res5[0x19fc - 0xa00];
 };
 
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLY__ */
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */