ARM: dts: stm32: Reinstate card detect behavior on ST boards

[oweals/u-boot.git] / arch / arm / dts / stm32mp157c-ed1-u-boot.dtsi

diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index b2ac49472a73017cf1818f9bae64987d416fca71..b16dc28d47a5daf635f80c22da3a83d46d654737 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -4,7 +4,7 @@
  */
 
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
-#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-u-boot.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
 / {
@@ -21,6 +21,20 @@
                st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
        };
 
+       firmware {
+               optee {
+                       compatible = "linaro,optee-tz";
+                       method = "smc";
+               };
+       };
+
+       reserved-memory {
+               optee@fe000000 {
+                       reg = <0xfe000000 0x02000000>;
+                       no-map;
+               };
+       };
+
        led {
                red {
                        label = "error";
@@ -28,10 +42,6 @@
                        default-state = "off";
                        status = "okay";
                };
-
-               blue {
-                       default-state = "on";
-               };
        };
 };
 
@@ -107,7 +117,7 @@
                CLK_UART6_HSI
                CLK_UART78_HSI
                CLK_SPDIF_PLL4P
-               CLK_FDCAN_PLL4Q
+               CLK_FDCAN_PLL4R
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q
@@ -121,6 +131,8 @@
 
        /* VCO = 1300.0 MHz => P = 650 (CPU) */
        pll1: st,pll@0 {
+               compatible = "st,stm32mp1-pll";
+               reg = <0>;
                cfg = < 2 80 0 0 0 PQR(1,0,0) >;
                frac = < 0x800 >;
                u-boot,dm-pre-reloc;
@@ -128,6 +140,8 @@
 
        /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
        pll2: st,pll@1 {
+               compatible = "st,stm32mp1-pll";
+               reg = <1>;
                cfg = < 2 65 1 0 0 PQR(1,1,1) >;
                frac = < 0x1400 >;
                u-boot,dm-pre-reloc;
@@ -135,6 +149,8 @@
 
        /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
        pll3: st,pll@2 {
+               compatible = "st,stm32mp1-pll";
+               reg = <2>;
                cfg = < 1 33 1 16 36 PQR(1,1,1) >;
                frac = < 0x1a04 >;
                u-boot,dm-pre-reloc;
@@ -142,6 +158,8 @@
 
        /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
        pll4: st,pll@3 {
+               compatible = "st,stm32mp1-pll";
+               reg = <3>;
                cfg = < 3 98 5 7 7 PQR(1,1,1) >;
                u-boot,dm-pre-reloc;
        };
@@ -149,11 +167,16 @@
 
 &sdmmc1 {
        u-boot,dm-spl;
+       broken-cd;
+       /delete-property/ cd-gpios;
 };
 
 &sdmmc1_b4_pins_a {
        u-boot,dm-spl;
-       pins {
+       pins1 {
+               u-boot,dm-spl;
+       };
+       pins2 {
                u-boot,dm-spl;
        };
 };