Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / dts / mt7629.dtsi

diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index e6052bbdcf3e5ef92639bcfd8f1dbe94daa7255a..6850e0058d485f54387de29bec0ad351120e1819 100644 (file)
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -10,6 +10,8 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/mt7629-power.h>
+#include <dt-bindings/reset/mt7629-reset.h>
+#include <dt-bindings/phy/phy.h>
 #include "skeleton.dtsi"
 
 / {
@@ -67,24 +69,21 @@
                compatible = "mediatek,mt7629-infracfg", "syscon";
                reg = <0x10000000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        pericfg: syscon@10002000 {
                compatible = "mediatek,mt7629-pericfg", "syscon";
                reg = <0x10002000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        timer0: timer@10004000 {
                compatible = "mediatek,timer";
                reg = <0x10004000 0x80>;
                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&topckgen CLK_TOP_10M_SEL>,
-                        <&topckgen CLK_TOP_CLKXTAL_D4>;
+               clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
+                        <&topckgen CLK_TOP_10M_SEL>;
                clock-names = "mux", "src";
-               u-boot,dm-pre-reloc;
        };
 
        scpsys: scpsys@10006000 {
@@ -102,7 +101,6 @@
                compatible = "mediatek,mt7629-mcucfg", "syscon";
                reg = <0x10200000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        sysirq: interrupt-controller@10200a80 {
@@ -123,21 +121,18 @@
                         <&topckgen CLK_TOP_MEM_SEL>,
                         <&topckgen CLK_TOP_DMPLL>;
                clock-names = "phy", "phy_mux", "mem", "mem_mux";
-               u-boot,dm-pre-reloc;
        };
 
        apmixedsys: clock-controller@10209000 {
                compatible = "mediatek,mt7629-apmixedsys";
                reg = <0x10209000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        topckgen: clock-controller@10210000 {
                compatible = "mediatek,mt7629-topckgen";
                reg = <0x10210000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        watchdog: watchdog@10212000 {
@@ -185,7 +180,6 @@
                status = "disabled";
                assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
                assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
-               u-boot,dm-pre-reloc;
        };
 
        uart1: serial@11003000 {
@@ -214,20 +208,107 @@
                status = "disabled";
        };
 
-       qspi: qspi@11014000 {
-               compatible = "mediatek,mt7629-qspi";
-               reg = <0x11014000 0xe0>, <0x30000000 0x10000000>;
-               reg-names = "reg_base", "mem_base";
+       snfi: snfi@1100d000 {
+               compatible = "mediatek,mtk-snfi-spi";
+               reg = <0x1100d000 0x2000>;
+               clocks = <&pericfg CLK_PERI_NFI_PD>,
+                        <&pericfg CLK_PERI_SNFI_PD>;
+               clock-names = "nfi_clk", "pad_clk";
+               assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+                                 <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+               assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+                                        <&topckgen CLK_TOP_UNIVPLL2_D8>;
                status = "disabled";
                #address-cells = <1>;
                #size-cells = <0>;
-               u-boot,dm-pre-reloc;
+       };
+
+       ssusbsys: ssusbsys@1a000000 {
+               compatible = "mediatek,mt7629-ssusbsys", "syscon";
+               reg = <0x1a000000 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       xhci: usb@1a0c0000 {
+               compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci";
+               reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>;
+               reg-names = "mac", "ippc";
+               power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
+               clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+                        <&ssusbsys CLK_SSUSB_REF_EN>,
+                        <&ssusbsys CLK_SSUSB_MCU_EN>,
+                        <&ssusbsys CLK_SSUSB_DMA_EN>;
+               clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+               phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+               status = "disabled";
+       };
+
+       u3phy: usb-phy@1a0c4000 {
+               compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x1a0c4000 0x1000>;
+               status = "disabled";
+
+               u2port0: usb-phy@0 {
+                       reg = <0x0 0x0700>;
+                       #phy-cells = <1>;
+                       clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+                       clock-names = "ref";
+               };
+
+               u3port0: usb-phy@700 {
+                       reg = <0x0700 0x0700>;
+                       #phy-cells = <1>;
+               };
        };
 
        ethsys: syscon@1b000000 {
                compatible = "mediatek,mt7629-ethsys", "syscon";
                reg = <0x1b000000 0x1000>;
                #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       eth: ethernet@1b100000 {
+               compatible = "mediatek,mt7629-eth", "syscon";
+               reg = <0x1b100000 0x20000>;
+               clocks = <&topckgen CLK_TOP_ETH_SEL>,
+                       <&topckgen CLK_TOP_F10M_REF_SEL>,
+                       <&ethsys CLK_ETH_ESW_EN>,
+                       <&ethsys CLK_ETH_GP0_EN>,
+                       <&ethsys CLK_ETH_GP1_EN>,
+                       <&ethsys CLK_ETH_GP2_EN>,
+                       <&ethsys CLK_ETH_FE_EN>,
+                       <&sgmiisys0 CLK_SGMII_TX_EN>,
+                       <&sgmiisys0 CLK_SGMII_RX_EN>,
+                       <&sgmiisys0 CLK_SGMII_CDR_REF>,
+                       <&sgmiisys0 CLK_SGMII_CDR_FB>,
+                       <&sgmiisys1 CLK_SGMII_TX_EN>,
+                       <&sgmiisys1 CLK_SGMII_RX_EN>,
+                       <&sgmiisys1 CLK_SGMII_CDR_REF>,
+                       <&sgmiisys1 CLK_SGMII_CDR_FB>,
+                       <&apmixedsys CLK_APMIXED_SGMIPLL>,
+                       <&apmixedsys CLK_APMIXED_ETH2PLL>;
+               clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
+                               "fe", "sgmii_tx250m", "sgmii_rx250m",
+                               "sgmii_cdr_ref", "sgmii_cdr_fb",
+                               "sgmii2_tx250m", "sgmii2_rx250m",
+                               "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+                               "sgmii_ck", "eth2pll";
+               assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
+                                 <&topckgen CLK_TOP_F10M_REF_SEL>;
+               assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
+                                        <&topckgen CLK_TOP_SGMIIPLL_D2>;
+               power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
+               resets = <&ethsys ETHSYS_FE_RST>;
+               reset-names = "fe";
+               mediatek,ethsys = <&ethsys>;
+               mediatek,sgmiisys = <&sgmiisys0>;
+               mediatek,infracfg = <&infracfg>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
        };
 
        sgmiisys0: syscon@1b128000 {
@@ -241,4 +322,20 @@
                reg = <0x1b130000 0x1000>;
                #clock-cells = <1>;
        };
+
+       pwm: pwm@11006000 {
+               compatible = "mediatek,mt7629-pwm";
+               reg = <0x11006000 0x1000>;
+               #clock-cells = <1>;
+               #pwm-cells = <2>;
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                        <&pericfg CLK_PERI_PWM_PD>,
+                        <&pericfg CLK_PERI_PWM1_PD>;
+               clock-names = "top", "main", "pwm1";
+               assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
+               assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>;
+               status = "disabled";
+       };
+
 };